JPS5961317A - Logical circuit - Google Patents

Abstract

PURPOSE:To eliminate the effect due to substrate bias effect by using the series connection of transistors(TRs) in the same number as the number of input terminals, for the same number of connections. CONSTITUTION:When input terminals A, B both go to ''H'', an output terminal C of an NAND circuit goes to ''L''. Switching TRsQ2A, Q2B causing substrate bias effect are connected to the input terminals A, B. Further, switching TRs Q1A, Q1B not causing the substrate bias effect are connected to the input terminals A, B. Thus, the effect of the substrate bias on the input terminals A, B is unified. Then, the input/output characteristic corresponding respectively to the input terminals A, B are unified.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a junction field effect transistor (J-FET).
, Schottky field effect transistor (MES-FET)
), MI S type field effect transistor (MI 5-
This invention relates to improvements in logic circuits composed of field effect transistors such as FETs.

BACKGROUND ART Conventionally, as a basic type of logic circuit using field effect transistors, a circuit realizing an AND function as shown in FIGS. 1 and 2 has been known.

The first bacterium is two people who are tent-based logic circuits.
(N to N I)) This is a circuit diagram of the main part of the circuit, and FIG. 2 is a diagram showing its logical symbols.

In the figure, △, B are input terminals, C is output glass, Ql,
Q2 is a switching transistor (the drive-side transistor group star is a load, Nl and N2 are connection points, I), S1 is a power supply terminal, and GNL) is a ground.

In this logic circuit, when a human power signal is input to both input terminals Δ and B, current flows through the load I, and a low level signal appears at the output terminal C, and the input terminal A.

When an input signal is applied to either of B or none of them, no current flows to the load, and a high level signal appears at the output terminal.

Now, when such a NAND circuit is realized on a semiconductor substrate, the substrate portions of switching transistors Q1 and Q2 are kept at the same potential as the ground GND. As a result, when the potential at the connection point N1 between switching transistors Q1 and Q2 changes during some switching process, the operating current of switching transistor Q2 changes due to a characteristic of field effect transistors known as the substrate bias effect.
A phenomenon occurs in which characteristics such as threshold voltage change as the potential of the connection point Nl changes. For this reason, the input terminal Δ.

When a signal is input to B, switching transistors Q1 and Q2 cannot exhibit the same input and output characteristics, which is a hindrance to the optimal stage d1 of the logic circuit.

This kind of thing is not only the case with the above-mentioned two-man power, but also the third one.
The same applies to systems that require three people to input, as shown in FIG. 4 and FIG.

Fig. 3 shows the main circuit diagram similar to Fig. 1, and Fig. 4 shows the logical symbol diagram of Fig. 3. The same parts as those explained in Fig. 1 and Fig. 2 are indicated by the same symbols. It is.

In the figure, a, b, c are input terminals, d is output terminal, Q
3 indicates switching transistors, respectively.

In this circuit, the switching transistor Q3 is most affected by the body bias effect, followed by the switching transistor Q2.

OBJECTS OF THE INVENTION The present invention is to prevent the characteristics of each switching transistor from becoming asymmetric due to the substrate high-speed effect in an AND logic circuit using field effect transistors.

Structure of the Invention In the present invention, in order to make the influence of the substrate bias effect the same for each switching transistor, similar buses are connected in the same number as the number of input terminals or in parallel to the bus in which each switching transistor is connected in series. Furthermore, switching transistors in each bus with different connection positions are selected one by one, and their gate electrodes are connected.

As a result, to any input terminal, a group of field effect transistors whose effects of the body bias effect are the same are connected as a whole, and therefore a group of switching transistors connected to each input terminal. There is no difference in input characteristics and output characteristics between the two, and since there is always one switching transistor corresponding to each signal in each series bus, the AND function is guaranteed.

Embodiment of the Invention FIG. 5 is a circuit diagram of a main part of an embodiment of the present invention, and the same parts as those explained in connection with FIGS. 1 and 2 are indicated by the same symbols.

In the figure, QIA, Q2A, QIB, and Q2B are switching transistors.

In this embodiment, switching transistors QIA and Q2A constitute one series bus, and switching transistors QIB and Q2B constitute another series bus. And, for early entry of input end, switching
Transistors Q2A and QIB are selected for input terminal B, and switch notching transistors QIA and Q2B are selected, respectively, and their respective gate electrodes are connected.

Therefore, switching transistor Q2A creates a body bias effect on input terminals A, B.

Switching transistors Q1Δ, QI with which Q2B- are connected and no body bias effect occurs
Since the input terminals A and B are connected to each other, the conditions for both input terminals A and B are exactly the same.

As seen in FIG. 5, even if two series paths are provided, each switching transistor CIA, QIB, Q2A,
By setting the gate width of Q2B to 1/2, the circuit current can be made the same as in the case of FIG. 1, and the circuit performance can also be made almost the same.

FIG. 6 is an explanatory plan view of the main parts when the circuit of FIG. 5 is viewed as a specific device, and the same parts as those explained in connection with FIG. 5 are indicated by the same symbols.

In the figure, AR is an active region, CH is a contact region,
CIA is the gate electrode of switching transistor QIA, GIB is the gate electrode of switching transistor QIB, G2A is the gate electrode of switching transistor Q2A, and G2B is switching transistor Q2.
The gate electrodes of B are shown respectively.

Gate electrodes GIA and GIB seen in FIG.

G2A and G2B may be considered to have a gate width of 1/2, as explained with reference to FIG.

That is, the gate electrode widths of both the gate electrodes CIA and GIB of the switching transistors Q1Δ and QIB are combined to form the switching transistor Q1 seen in FIG.
The width of the gate electrode of the switching transistor Q2A and Q2B may be approximately the same as the width of the gate electrode of the switching transistor Q2 shown in FIG.

Although the above-mentioned embodiment is a case in which two people are involved, the present invention can be similarly applied to a case in which the number of inputs is larger than that.

FIG. 7 is a circuit diagram of the main part of the embodiment which is powered by three people.
The same parts as those described with reference to FIGS. 6 to 6 are indicated by the same symbols.

In the figure, QIC, Q2C, Q3A, Q3B.

Q3C is a switching transistor, a, b.

C indicates an input terminal, and d indicates an output terminal.

In this embodiment, although it is powered by three people, there are three serial buses. Then, each gate electrode of the three selected switching transistors is connected to one input from each series path. As a result, each switching transistor group associated with each input terminal has balanced characteristics.In the illustrated example, the switching transistors
Transistors QIA, Q3B, Q2C, switching
Transistor Q28, QIB, Q3C, switching
Transistors Q3A, Q2B, and QIC are combined as a group, and their respective gate electrodes are connected.

In this embodiment, if the overall operating current is to be approximately the same as that shown in FIGS. 3 and 4, the width of the gate electrode of each switching transistor may be selected to be 1/3. .

Effects of the Invention According to the present invention, in a logic circuit in which a plurality of switching transistors, which are field effect transistors, are connected in series to realize an AND system function, the series connection circuit of the switching transistors is connected in series to reduce the number of input terminals. Select one switching transistor with a different connection position from the series-connected circuit, connect the gate electrodes of the switching transistors, and form a group of switching transistors. Since the switching transistor groups are connected in correspondence with the input terminals, when each switching transistor group connected to each input terminal is viewed as one switching transistor, the switching transistors receive The substrate bias effect is the same, and the disadvantage that the output characteristics differ depending on which input terminal the signal is input to is eliminated.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of the main part of a conventional example, Fig. 2 is a logic symbol diagram of the circuit of Fig. 1, Fig. 3 is a circuit diagram of main part of another conventional example.
3 is a logical symbol diagram of the circuit, FIG. 5 is a circuit diagram of the main part of the present invention-embodiment, FIG. FIG. 7 is a main circuit diagram of another embodiment. In the figure, A and B are input terminals, C is an output terminal, Q18, Q2A, QIB, and Q2B are switching terminals, L is a load, and GND is a ground. Patent applicant Fujitsu Ltd. Representative Patent Attorney Kugobe Tamamushi (3 others) Figure 1 Figure 3

Claims (1)

[Claims] In a logic circuit that realizes an AND system function by connecting a plurality of switching transistors, which are field effect transistors, in series, a series connection circuit of the switching L-transistors is installed in a number corresponding to the number of input terminals. Switching circuits with different connection positions from series-connected circuits
A logic circuit characterized in that a group of transistors are selected and their gate electrodes are connected to form a switching transistor group, and the switching transistor group is connected in correspondence with the input terminal.