KR950034618A - Method for manufacturing a side dipole transistor device having a complete device isolation structure - Google Patents

Method for manufacturing a side dipole transistor device having a complete device isolation structure Download PDF

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KR950034618A
KR950034618A KR1019940010555A KR19940010555A KR950034618A KR 950034618 A KR950034618 A KR 950034618A KR 1019940010555 A KR1019940010555 A KR 1019940010555A KR 19940010555 A KR19940010555 A KR 19940010555A KR 950034618 A KR950034618 A KR 950034618A
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layer
forming
insulating film
silicon
photoresist pattern
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KR0128023B1 (en
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이경수
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양승택
재단법인 한국전자통신연구소
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6625—Lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H01L29/0808—Emitter regions of bipolar transistors of lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H01L29/1008—Base region of bipolar transistors of lateral transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
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  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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  • Bipolar Transistors (AREA)

Abstract

본 발명은 SOI(silicon-on-insulator)기판 위에서 에미터와 베이스, 콜렉터를 활성영역에 측면으로 배열하여 기생저항 및 기생용량을 감소시킬 수 있는 측면 쌍극자 트랜지스터(lateral bipolar transistor)장치의 제조 방법에 관한 것으로, 소자격리를 수행하고, 에미터아 서브-콜렉터 부분인 n++영역(22)을 정의하고, 반응성 이온식각법으로 n++(22)의 실리콘산화막(14)을 식각하며, 실리콘질화막을 형성하고 반응성 이온식각법으로 실리콘질화막을 비등방성으로 식각하여 측벽 실리콘질화막(15)을 형성하며, n++영역(16)을 형성하기 위해서 n형 불순물을 이온주입(17)하고, 열산화하여서 n++(16)에 실리콘산화막(18)을 형성하며, 베이스영역을 정의하고, 측벽 실리콘질화막(15)을 완전히 제거하고, 이온주입(110)하여 베이스층(111)을 형성하고 감광막을 제거하며, in-sit doping 화학증착법으로 이용하여 실리콘층이 노출되어 있는 베이스영역(111)에만 선택적으로 p++실리콘층(112)을 성장시키며, 실리콘산화막(113)을 형성하고 열처리함으로서 주입된 불순물을 활성화시키고, 에미터와베이스의 접합(114)을 형성한 후, 접촉부분(24)을 정의하고, 정의된 감광막을 마스크로 반응성 이온 식각하여 실리콘산화막(113,18)을 식각하고 감광막을 제거하며, 타이타늄을 형성하고 열처리하여 타이타늄 실리사이드(114)를 형성하고, 남은 타이타늄을 완전 제거한 후, 전극용 금속(알루미늄)을 형성하고 전극형상(25)을 정의하고 식각하여 열처리함으로써 전극(115)을 형성한다.The present invention relates to a method of manufacturing a lateral bipolar transistor device capable of reducing parasitic resistance and parasitic capacitance by arranging emitters, bases, and collectors in an active region laterally on a silicon-on-insulator (SOI) substrate. In this regard, device isolation is performed, the n ++ region 22, which is an emitter sub-collector, is defined, and the silicon oxide film 14 of n ++ 22 is etched by reactive ion etching, and the silicon nitride film The silicon nitride film is anisotropically etched by reactive ion etching to form the sidewall silicon nitride film 15, and ion implantation 17 of the n-type impurities to form the n ++ region 16, and thermal oxidation To form a silicon oxide film 18 on n ++ 16, define a base region, completely remove the sidewall silicon nitride film 15, and ion implant 110 to form a base layer 111 to form a photoresist film. In-sit doping Using the crane deposition sikimyeo growth selectively p ++ silicon layer 112 only in the base region 111 which is a silicon layer is exposed, to form a silicon oxide film 113 and activate the implanted impurities by heat treatment, an emitter After forming the junction 114 of the wafer base, the contact portion 24 is defined, and reactive ion etching is performed using the defined photoresist film to etch the silicon oxide films 113 and 18, remove the photoresist film, and form titanium. After heat treatment to form the titanium silicide 114, the remaining titanium is completely removed, and then the electrode 115 is formed by forming a metal for the electrode (aluminum), defining the electrode shape 25, and etching and heat treating the electrode.

Description

완전 소자 격리구조를 갖는 측면 쌍극자 트랜지스터장치의 제조방법Method for manufacturing a side dipole transistor device having a complete device isolation structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도의 (a)~(1)은 본 발명의 바람직한 실시예에 따른 측면 쌍극자 트랜지스터의 제조방법을 공정순서대로 나타낸 단면도이다.(A)-(1) is sectional drawing which shows the manufacturing method of the side dipole transistor which concerns on a preferable embodiment of this invention in process order.

Claims (4)

절연막(11)과, 그 위에 얇게 형성된 제1도전형의 실리콘층(12)을 갖는 SOI기판을 사용하여 반도체 장치를 제조하는 방법에 있어서; 열 산화에 의해 상기 제1도전형의 실리콘층(12)에 소자격리용 절연막(13)을 형성하고, 상기 실리콘층(12)의 표면 위에 2000A정도의 두께로 제1절연막(14)을 형성하는 공정과; 리소그라피에 의해 활성영역을 정의하여 감광막 패턴을 형성하고, 상기 감광막 패턴을 마스크로서 사용하는 반응성 이온식각(RIE)에 의해 상기 절연막(14)의 표면위에 화학증착법에 의해 제2절연막을 형성하고, 반응성 이온 식각법으로 상기 제2절연막을 비등방적으로 식각함으로써, 측벽 절연막(15)을 형성함과 아울러 상기 실리콘층(12)을 노출시키는 공정과; 상기 노출된 실리콘층(12)으로 제1도전형의 불순물 이온(17)을 고농도로 주입하여 한쌍의 제1도전층들(16)을 형성하는 공정과; 선택적인 열산화에 의해 상기 제1도전층들(16) 위에만 선택적으로 제3절연막(18)을 형성하고, 리소그라피에 의해 베이스를 정의하여 감광막 패턴(19)을 형성한 후 상기 감광막 패턴(19)을 마스크로서 사용하는 식각에 의해 베이스가 형성될 영역에 위치한 측벽 절연막(15a)을 완전히 제거하여 상기 실리콘층(12)의 표면을 노출시키는 공정과; 상기 제1 및 제3절연막(14,18)을 마스크로서 사용하는 이온 주입에 의해 제2도전형의 불순물(110)을 상기 노출된 실리콘층(12)으로 주입하여 제2도전층(111)를 형성하는 공정과; 화학증착법으로 표면이 노출된 상기 제2도전층(111)주위에만 제2도전형의 불순물이 고농도로 도핑된 제3도전층(112)을 형성하는 공정과; 웨이퍼의 전 표면 위에 제4절연막(113)을 형성하고, 열처리를 수행하여 주입된 불순물을 활성화시키는 공정과; 리소그라피방법으로 접촉영역을 정의하여 감광막 패턴을 형성하고, 상기 감광막 패턴을 마스크로서 사용하여 상기 제4 및 제3절연막(113,18)을 식각하여 상기 제1도전층들(16)의 표면을 노출시킨 후 상기 감광막 패턴을 제거하는 공정과; 웨이퍼의 표면 위에 타이타늄층을 형성하고, 열처리를 수행하여 상기 제1도전층들(16) 위에 타이타늄 실리사이드층(114)을 형성한 후 상기 제4절연막(113) 위에 형성된 상기 타이타늄층을 제거하는 공정과; 웨이퍼의 표면 위에 금속층을 형성하고 감광막을 도포한 후, 리소그라피 방법으로 금속 전극 형상을 정의하여 감광막 패턴을 형성하고 상기 감광막 패턴을 마스크로서 사용하여 금속층을 식각하는 것에 의해 에미터, 베이스, 콜렉터의 금속전극(115)을 각각 형성한 후 열처리하는 공정을 포함하는 것을 특징으로 하는 완전 소자 격리구조를 갖는 측면 쌍극자 트랜지스터 장치의 제조방법.A method of manufacturing a semiconductor device using an SOI substrate having an insulating film (11) and a first conductive silicon layer (12) thinly formed thereon; Forming a device isolation insulating film 13 in the silicon layer 12 of the first conductive type by thermal oxidation, and forming the first insulating film 14 on the surface of the silicon layer 12 with a thickness of about 2000 A. Process; A photoresist pattern is formed by defining an active region by lithography, and a second insulating layer is formed on the surface of the insulating layer 14 by chemical vapor deposition by reactive ion etching (RIE) using the photoresist pattern as a mask. Anisotropically etching the second insulating film to form a sidewall insulating film 15 and to expose the silicon layer 12; Implanting a high concentration of impurity ions 17 of a first conductivity type into the exposed silicon layer 12 to form a pair of first conductive layers 16; A third insulating film 18 is selectively formed only on the first conductive layers 16 by selective thermal oxidation, and a photoresist pattern 19 is formed by defining a base by lithography to form the photoresist pattern 19. Exposing the surface of the silicon layer 12 by completely removing the sidewall insulating film 15a located in the region where the base is to be formed by etching using a mask as a mask; The second conductive layer 111 is formed by implanting the second conductive type impurity 110 into the exposed silicon layer 12 by ion implantation using the first and third insulating layers 14 and 18 as masks. Forming step; Forming a third conductive layer (112) doped with a high concentration of impurities of a second conductivity type only around the second conductive layer (111) whose surface is exposed by chemical vapor deposition; Forming a fourth insulating film 113 on the entire surface of the wafer and performing heat treatment to activate the implanted impurities; A contact region is defined by a lithography method to form a photoresist pattern, and the fourth and third insulating layers 113 and 18 are etched using the photoresist pattern as a mask to expose the surfaces of the first conductive layers 16. Removing the photoresist pattern after the step; Forming a titanium layer on the surface of the wafer, performing a heat treatment to form a titanium silicide layer 114 on the first conductive layers 16, and then removing the titanium layer formed on the fourth insulating layer 113. and; After forming a metal layer on the surface of the wafer and applying a photoresist film, a metal electrode shape is defined by a lithography method to form a photoresist pattern, and the metal layer is etched using the photoresist pattern as a mask to etch the metal of the emitter, base, and collector. A method of manufacturing a side dipole transistor device having a complete device isolation structure, comprising: forming an electrode (115) and then performing heat treatment. 제1항에 있어서, 상기 제1, 제32, 및 제4절연막을 실리콘 산화막으로 형성되고, 상기 제2절연막은 실리콘질화막으로 형성되는 것을 특징으로 하는 완전 소자 격리구조를 갖는 측면 쌍극자 트랜지스터 장치의 제조방법.The side dipole transistor device of claim 1, wherein the first, 32, and fourth insulating films are formed of a silicon oxide film, and the second insulating film is formed of a silicon nitride film. Way. 제1항 또는 제2항에 있어서, 상기 측벽 절연막(15)은 베이스(111)의 폭 크기에 상응하는 두깨로 형성되는 것을 특징으로 하는 완전 소자 격리구조를 갖는 측면 쌍극자 트랜지스터 장치의 제조방법.A method according to claim 1 or 2, wherein the sidewall insulating film (15) is formed with a thickness corresponding to the width of the base (111). 제1항에 있어서, 상기 제2도전층(112)의 형성공정은 화학증착법으로 표면이 노출된 상기 베이스 영역(111)에만 선택적으로 3000A정도의 두께로 실리콘층(112)을 성정시킴과 동시에 거기로 p++형의 불순물의 주입하는 공정을 포함하는 것을 특징으로 하는 완전 소자 격리구조를 갖는 측면 쌍극자 트랜지스터 장치의 제조방법.The method of claim 1, wherein the forming of the second conductive layer 112 is performed by chemical vapor deposition, and at the same time, the silicon layer 112 is formed to a thickness of about 3000 A selectively only in the base region 111 where the surface is exposed. And a step of implanting a p ++ type impurity. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940010555A 1994-05-14 1994-05-14 Fabrication method of lateral bipolar transistor device complete element isolation structure KR0128023B1 (en)

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