KR950034453A - Method for manufacturing a side dipole transistor device - Google Patents

Method for manufacturing a side dipole transistor device Download PDF

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KR950034453A
KR950034453A KR1019940010554A KR19940010554A KR950034453A KR 950034453 A KR950034453 A KR 950034453A KR 1019940010554 A KR1019940010554 A KR 1019940010554A KR 19940010554 A KR19940010554 A KR 19940010554A KR 950034453 A KR950034453 A KR 950034453A
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layer
film
silicon
oxide film
photoresist pattern
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KR0128024B1 (en
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이경수
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양승택
재단법인 한국전자통신연구소
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6625—Lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H01L29/0808—Emitter regions of bipolar transistors of lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H01L29/1008—Base region of bipolar transistors of lateral transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Bipolar Transistors (AREA)

Abstract

본 발명은 SOI(silicon-on-insulator)기판 위에서 완전히 소자격리되고, 에미터와 베이스, 콜렉터가 수평으로 배치되는 측면 쌍극자 트랜지스터(lateral bipolar transistor)장치의 제조방법에 관한 것이다. 열산화에 의한 완전한 소자격리(13)를 하고, 규소질화막(14)과 규소산화막(15)을 순차적으로 도포하며, 베이스영역(22)을 정의하고, 반응성 이온 식각법으로 베이스영역(22)의 규소산화막(15)과 규소질화막(14)을 식각하며, 산화막을 도포하고 반응성 이온 식각법으로 규소질화막을 비등방성으로 식각하여 측벽 규소질화막(16)을 형성하며, 베이스층(18)에 p형 불순물을 이온주입(17)하며, 즉석도핑(in-situ doping)화학증착법을 이용하여 규소층이 노출되어 있는 베이스층(18)에만 선택적으로 p++규소층(19)을 성장시키며, 규소산화막(15)을 식각 제거하고, 선택적으로 성장된 p++규소층(19)에만 열산화에 이한 규소산화막(110)을 성장하며, 에미터와 n++서브-콜렉터 형성을 위한 n++영역(23)을 정의하고, 정의된 감광막(111)을 마스크로 n형 불순물을 이온주입(112)하며, 감광막(111)을 제거하고, 규소산화막(116)을 도포하고 열처리함으로써 주입된 불순물을 활성화시키고, 에미터(117)와 베이스(118)의 접합(119)형성하며, 접촉부분(24)을 정의하고, 정의된 감광막을 마스크로 반응성 이온 식각하여 규소산화막(116)과 규소질화막(14)을 식각하고 감광막(120)을 제거하며, 타이타늄을 도포하고 열처리하여 타이타늄 규화물(121)을 형성하고, 남은 타이타늄을 완전 제거한 후, 전극용 금속(알루미늄)을 도포하고 전극형상(25)을 정의하고 식각하여 열처리함으로써 전극(122)을 형성하여, 동작속도를 크게 향상시킬 수 있으며, MOSFET소자의 비슷한 수준의 높은 집적도를 얻을 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a lateral bipolar transistor device in which a device is completely isolated on a silicon-on-insulator substrate and an emitter, a base, and a collector are horizontally disposed. Complete device isolation 13 by thermal oxidation is performed, the silicon nitride film 14 and the silicon oxide film 15 are sequentially applied, the base area 22 is defined, and the reactive ion etching method of the base area 22 is performed. The silicon oxide film 15 and the silicon nitride film 14 are etched, the oxide film is coated, and the silicon nitride film is anisotropically etched by reactive ion etching to form the sidewall silicon nitride film 16, and the p-type is formed on the base layer 18. Impurities are ion implanted (17), and the p ++ silicon layer (19) is selectively grown only on the base layer (18) where the silicon layer is exposed by in-situ doping chemical vapor deposition. (15) is etched away, and only the selectively grown p ++ silicon layer 19 is grown on the silicon oxide film 110 followed by thermal oxidation, and the n ++ region for the formation of the emitter and the n ++ sub-collector (23), ion implantation 112 of n-type impurities using the defined photosensitive film 111 as a mask, and The film 111 is removed, the silicon oxide film 116 is applied and heat treated to activate the implanted impurities, to form the junction 119 of the emitter 117 and the base 118, and to define the contact portion 24. Reactive ion etching is performed using the defined photoresist film as a mask to etch the silicon oxide film 116 and the silicon nitride film 14, to remove the photoresist film 120, and to apply titanium and heat treatment to form the titanium silicide 121. After the titanium is completely removed, the electrode 122 is formed by applying an electrode metal (aluminum), defining the electrode shape 25, and etching and heat-treating it to greatly improve the operation speed. High integration can be obtained.

Description

측면 쌍극자 트랜지스터 장치의 제조방법Method for manufacturing a side dipole transistor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도의 (a) 내지 (k)는 본 발명에 따른 측면 쌍극자 트랜지스터의 제조방법을 공정별로 나타낸 단면도이다.(A) to (k) of FIG. 1 are cross-sectional views showing the manufacturing method of the side dipole transistor according to the present invention for each step.

Claims (3)

SOI(silicon-on-insulator)기판을 이용한 반도체 장치의 제조방법에 있어서; n-형의 규소층(12)이 절연층(11) 위에 형성된 SOI 기탄에 소자격리를 위한 제1절연막(13)을 형성하고, 화학증착법(CVD)에 의해 질화막(14)과 산화막(15)을 각각 순차적으로 형성하는 공정과; 리소그라피에 의해 베이스 영역(22)을 정의하고, 반응성 이온 식각에 의해 상기 산화막(15)과 상기 질화막(14)을 순차적으로 식각하여 상기 n-형의 규소층(12)의 표면을 노출시키는 공정과; 웨이퍼의 전 표면 위에 제2절연막을 형성하고 비등방성식각을 수행하여 측벽 절연막(16)을 형성한 후, 상기 규소층(12)의 노출된 표면으로 p형 불순물을 주입하여(17) 베이스층(18)을 형성하는 공정과; 상기 베이스층(18) 위에만 선택적으로 도전층(19)을 형성하고, 남아있는 상기 산화막(15)을 제거하는 공정과; 열산화에 의해 상기 도전층(19)위에 제3절연막(110)을 성장시키고, 리소그라피방법으로 에미터와 서브-콜렉터로 사용될 n++형의 영역(23,113)을 정의하여 감광막 패턴(111)을 형성하고, 상기 감광막 패턴(111)을 마스크로서 사용하여 상기 질화막(14)을 통해 상기 규소층(12)으로 불순물 이온(112)을 주입하는 공정과; 감광막 패턴(111)을 제거하고, 웨이퍼의 전 표면 위에 제4절연막(116)을 형성한 후, 열처리에 의해 주입된 불순물들을 활성화시켜 접합(119)을 형성하는 공정과; 리소그라피에 의해 접촉영역(24)을 정의하여 감광막 패턴(120)을 형성하고, 상기 감광막 패턴(120)을 마스크로서 사용하여 상기 제4절연막(116)과 상기 질화막(14)을 순차적으로 식각한 후 상기 감광막 패턴(120)을 제거하는 공정과; 웨이퍼의 전 표면 위에 타이타(titanium)을 도포하고 열처리하여 타이타늄 규화물(121)을 생성하고, 상기 산화막(116)위에 남아 있는 상기 타이타늄을 완전히 제거하는 공정과; 웨이퍼의 표 면 위에 금속층을 형성한 후 리소그라피 방법으로 금속전극패턴을 정의하여 감광막 패턴을 형성하고, 감광막 패턴을 마스크로서 사용하여 상기 금속층을 식각하는 것에 의해 금속전극(122)을 각각 형성하고 열처리하는 공정을 포함하는 것을 특징으로 하는 측면 쌍극자 트랜지스터 장치의 제조방법.A method of manufacturing a semiconductor device using a silicon-on-insulator (SOI) substrate; The n − type silicon layer 12 forms a first insulating film 13 for device isolation on SOI carbon formed on the insulating layer 11, and the nitride film 14 and the oxide film 15 by chemical vapor deposition (CVD). Forming each sequentially; Defining a base region 22 by lithography and sequentially etching the oxide film 15 and the nitride film 14 by reactive ion etching to expose the surface of the n − type silicon layer 12; ; After forming the second insulating film on the entire surface of the wafer and performing anisotropic etching to form the sidewall insulating film 16, p-type impurities are implanted into the exposed surface of the silicon layer 12 (17) 18) forming; Selectively forming a conductive layer (19) only on the base layer (18) and removing the remaining oxide film (15); The third insulating layer 110 is grown on the conductive layer 19 by thermal oxidation, and n + type regions 23 and 113 to be used as emitters and sub-collectors are defined by lithography to define the photoresist pattern 111. Forming and implanting impurity ions (112) into the silicon layer (12) through the nitride film (14) using the photoresist pattern (111) as a mask; Removing the photoresist pattern 111, forming a fourth insulating film 116 on the entire surface of the wafer, and then activating the impurities implanted by the heat treatment to form a junction 119; After the contact region 24 is defined by lithography to form the photoresist pattern 120, the fourth insulating layer 116 and the nitride layer 14 are sequentially etched using the photoresist pattern 120 as a mask. Removing the photoresist pattern (120); Applying titanium over the entire surface of the wafer and heat-treating to form titanium silicide 121 and completely removing the titanium remaining on the oxide film 116; After forming a metal layer on the surface of the wafer, a metal electrode pattern is defined by a lithography method to form a photoresist pattern, and the metal layer 122 is formed and heat treated by etching the metal layer using the photoresist pattern as a mask. A process for producing a lateral dipole transistor device, comprising the step of; 제1항에 있어서, 상기 도전층(19)은 규소층으로 이루어지며, 상기 베이스층(18)위에 형성될 때 즉석(in-situ)도핑에 의해 p++형의 불순물이 주입되는 것을 특징으로 하는 측면 쌍극자 트랜지스터 장치의 제조방법.The method of claim 1, wherein the conductive layer 19 is made of a silicon layer, when formed on the base layer 18 is characterized in that the impurity of the p + + type is implanted by in-situ doping A method of manufacturing a side dipole transistor device. 제1항 또는 제2항에 있어서, 상기 베이스층(18)은 상기 측벽절연막(16)에 의해 정의되는 상기 베이스영역(22)의 폭 보다 더 좁은 폭으로 형성되는 것을 특징으로 하는 측면 쌍극자 트랜지스터 장치의 제조방법.The side dipole transistor device according to claim 1 or 2, wherein the base layer (18) is formed to have a width narrower than the width of the base region (22) defined by the sidewall insulating film (16). Manufacturing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940010554A 1994-05-14 1994-05-14 Fabrication method of cateral bipolar transistor device KR0128024B1 (en)

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KR1019940010554A KR0128024B1 (en) 1994-05-14 1994-05-14 Fabrication method of cateral bipolar transistor device

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KR0128024B1 KR0128024B1 (en) 1998-04-06

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