KR950034595A - Oxide film formation method of semiconductor device - Google Patents

Oxide film formation method of semiconductor device Download PDF

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Publication number
KR950034595A
KR950034595A KR1019940011479A KR19940011479A KR950034595A KR 950034595 A KR950034595 A KR 950034595A KR 1019940011479 A KR1019940011479 A KR 1019940011479A KR 19940011479 A KR19940011479 A KR 19940011479A KR 950034595 A KR950034595 A KR 950034595A
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South Korea
Prior art keywords
oxide film
forming
semiconductor device
gas
film
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KR1019940011479A
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Korean (ko)
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KR0119965B1 (en
Inventor
박인옥
서광수
이성수
정영석
김의식
홍흥기
구영모
김세정
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김주용
현대전자산업 주식회사
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Priority to KR1019940011479A priority Critical patent/KR0119965B1/en
Publication of KR950034595A publication Critical patent/KR950034595A/en
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Publication of KR0119965B1 publication Critical patent/KR0119965B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 반도체 소자의 산화막 형성방법에 관한 것으로, 반도체 소자의 제조공정중 게이트 산화막 또는 층간 절연 산화막을 형성함에 있어, LPCVD 장비에서 CVD 방식으로 SiH4개스와 N2O 개스를 이용하여 산화막을 증착시킨 후 동일한 장비에서 연속적으로 N2O 개스를 이용하여 어닐링(Annealing)을 진행하므로써 양질의 산화막을 얻을 수 있는 반도체 소자의 산화막 형성방법에 관한 것이다.The present invention relates to a method of forming an oxide film of a semiconductor device, in forming a gate oxide film or an interlayer insulating oxide film during a semiconductor device manufacturing process, depositing an oxide film using SiH 4 gas and N 2 O gas by CVD in an LPCVD apparatus. The present invention relates to a method for forming an oxide film of a semiconductor device in which a high quality oxide film can be obtained by annealing using N 2 O gas continuously in the same equipment.

Description

반도체 소자의 산화막 형성방법Oxide film formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1C도는 본 발명에 의한 반도체 소자의 산화막 형성방법을 설명하기 위해 도시한 단면도.1A to 1C are cross-sectional views for explaining the oxide film forming method of a semiconductor device according to the present invention.

Claims (6)

반도체 소자의 산화막 형성방법에 있어서, 증착장비 내부를 소정의 온도와 저압상태로 하고, SiH4개스와 N2O 개스를 동시에 주입하면서 CVD 방식의 소정의 기판상에 산화막(2)을 증착시키는 단계와, 상기 단계로부터 SiH4개스 주입을 중단하고, 소정의 온도로 상승시킨 후 N2O 개스만을 계속 주입하면서 상기 증착된 산화막(2)을 어닐링하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 산화막 형성방법.A method of forming an oxide film of a semiconductor device, the method comprising: depositing an oxide film 2 on a predetermined substrate of a CVD method while simultaneously injecting SiH 4 gas and N 2 O gas into a predetermined temperature and a low pressure state in a deposition apparatus. And annealing the deposited oxide film 2 while stopping injection of SiH 4 gas from the above step, raising the temperature to a predetermined temperature, and continuing injecting only N 2 O gas. Way. 제1항에 있어서, 상기 산화막(2)은 트랜지스터의 게이트 산화막인 것을 특징으로 하는 반도체 소자의 산화막 형성방법.The method of forming an oxide film of a semiconductor device according to claim 1, wherein said oxide film (2) is a gate oxide film of a transistor. 제1항에 있어서, 상기 산화막(2)은 폴리실리콘과 폴리실리콘 사이를 절연하는 층간절연 산화막인 것을 특징으로 하는 반도체 소자의 산화막 형성방법.The method of forming an oxide film of a semiconductor device according to claim 1, wherein said oxide film (2) is an interlayer insulating oxide film insulating between polysilicon and polysilicon. 제1항에 있어서, 상기 산화막(2) 증착공정시 온도는 700∼800℃, 압력은 1Torr미만이며, 상기 증착된 산화막(2)의 어닐링공정시 온도는 800∼900℃인 것을 특징으로 하는 반도체 소자의 산화막 형성방법.The semiconductor according to claim 1, wherein the temperature during the deposition process of the oxide film 2 is 700 to 800 ° C, the pressure is less than 1 Torr, and the temperature during the annealing process of the deposited oxide film 2 is 800 to 900 ° C. A method of forming an oxide film of a device. 제1항에 있어서, 상기 N2O 개스 분위기로 어닐링공정을 진행할 때 질소이온이 산화막(2)으로 확산되어 하부 기판과의 경계면에 새로운 구조의 경계막(3)을 형성시키는 것을 특징으로 하는 반도체 소자의 산화막 형성방법.The semiconductor according to claim 1, wherein when the annealing process is performed in the N 2 O gas atmosphere, nitrogen ions diffuse into the oxide film 2 to form a boundary film 3 having a new structure on the interface with the lower substrate. A method of forming an oxide film of a device. 제5항에 있어서, 상기 경계막(3)은 SixOyNz구조인 것을 특징으로 하는 반도체 소자의 산화막 형성방법.The method of forming an oxide film of a semiconductor device according to claim 5, wherein the boundary film (3) has a S ix O y N z structure. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940011479A 1994-05-26 1994-05-26 Oxidation method of semiconductor device KR0119965B1 (en)

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Application Number Priority Date Filing Date Title
KR1019940011479A KR0119965B1 (en) 1994-05-26 1994-05-26 Oxidation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940011479A KR0119965B1 (en) 1994-05-26 1994-05-26 Oxidation method of semiconductor device

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KR950034595A true KR950034595A (en) 1995-12-28
KR0119965B1 KR0119965B1 (en) 1997-10-17

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100282413B1 (en) * 1996-10-24 2001-03-02 김영환 Thin film formation method using nitrous oxide gas
KR100332129B1 (en) * 1995-12-29 2002-11-07 주식회사 하이닉스반도체 Method for forming oxide layer in semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100332129B1 (en) * 1995-12-29 2002-11-07 주식회사 하이닉스반도체 Method for forming oxide layer in semiconductor device
KR100282413B1 (en) * 1996-10-24 2001-03-02 김영환 Thin film formation method using nitrous oxide gas

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KR0119965B1 (en) 1997-10-17

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