KR950033839A

KR950033839A - Address blocking circuit

Info

Publication number: KR950033839A
Application number: KR1019940010486A
Authority: KR
Inventors: 변형남
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1994-05-13
Filing date: 1994-05-13
Publication date: 1995-12-26

Abstract

본 발명은 어드레스 차단회로를 공개한다. 그 회로는 현재의 리드 어드레스 인에이블 신호에 응답하여 현재의 리드 어드레스를 발생하고 다음의 리드 어드레스 인에이블 신호에 응답하여 다음의 리드 어드레스를 발생하기 위한 리드 어드레스 발생수단, 현재의 라이트 어드레스 인에이블 신호에 응답하여 현재의 라이트 어드레스르르 발생하고 다음의 라이트 어드레스 인에이블 신호에 응답하여 다음의 라이트 어드레스를 발생하기 위한 라이트 어드레스 발생수단, 상기 현재의 라이트 어드레스와 상기 다음의 리드 어드레스를 비교하여 동일하면 상기 리드 어드레스 발생수단의 다음의 리드 어드레스 증가를 막기 위한 리드 어드레스 차단수단, 상기 현재의 리드 어드레스와 상기 다음의 라이트 어드레스를 비교하여 동일하면 상기 라이트 어드레스 발생수단의 다음의 라이트어드레스 증가를 막기 위한 라이트 어드레스 차단수단, 상기 현재의 라이트 어드레스 인에이블 신호에 응답하여 상기 라이트 어드레스 발생수단으로 부터의 현재의 라이트 어드레스를 어드레스로 출력하고 상기 현재의 리드 어드레스 인에이블 신호에 응답하여 상기 리드 어드레스 발생수단으로 부터의 현재의 리드 어드레스를 어드레스로 출력하기 위한 어드레스 발생수단으로 구성되어 있다. 따라서, 메모리 셀내에 데이타를 오버라이트하는 것을 방지할 수 있다.The present invention discloses an address blocking circuit. The circuit includes read address generation means for generating a current read address in response to a current read address enable signal and generating a next read address in response to a next read address enable signal, a current write address enable signal. A write address generating means for generating a current write address in response to the next write address and generating a next write address in response to a next write address enable signal, comparing the current write address with the next read address if the same; A read address blocking means for preventing the next read address increase of the read address generating means, and comparing the current read address with the next write address, and if the same, increases the next write address of the write address generating means. A write address blocking means for outputting a current write address from the write address generating means as an address in response to the current write address enable signal and generating the read address in response to the current read address enable signal. Address generation means for outputting the current read address from the means as an address. Therefore, overwriting of data in the memory cell can be prevented.

Description

Address blocking circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 어드레스 차단회로의 블록도이다.1 is a block diagram of an address blocking circuit of the present invention.

Claims

Next read address generating means for generating a current read address in response to a current read address enable signal; Read address generation means for generating a next read address in response to the current write address signal; Write address generating means for generating a current write address in response to a current write address enable signal and generating a next write address in response to a next write address enable signal; Read address blocking means for preventing the increase of the next read address of the read address generating means if the current write address is compared with the next read address; Write address blocking means for preventing the increase of the next write address of the write address generating means if the current read address is compared with the next write address; Outputs a current write address from the write address generating means to an addresser in response to the current write address enable signal and a current read from the read address generating means in response to the current read address enable signal And an address generating means for outputting the address as an address.

The address blocking circuit according to claim 1, wherein the write address generating means sequentially increases the read address by one.

The address blocking circuit according to claim 1, wherein the write address generating means sequentially increases the write address by one.

2. The apparatus of claim 1, wherein the read address blocking means comprises: initialization means for initializing a read address upon initial address transmission; An address blocking circuit further comprising an address increasing means for naturally increasing a read address held and blocked.

A read address generating step of generating a current read address in response to a current read address enable signal and generating a next read address in response to a next read address enable signal; A write address generating step of generating a current write address in response to a current write address enable signal and generating a next write address in response to a next write address enable signal; A read address blocking step for preventing the increase of the read address if the current write address is compared with the next read address; A write address blocking step of comparing the current read address with the next write address and preventing an increase in the write address if the read address is the same; And an address generating step of outputting the current write address as an address in response to the current write address enable signal and outputting the current read address as an address in response to the current read address enable signal. Address blocking method.

※ Note: The disclosure is based on the initial application.