KR950028003A - Semiconductor devices - Google Patents

Semiconductor devices Download PDF

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Publication number
KR950028003A
KR950028003A KR1019940005953A KR19940005953A KR950028003A KR 950028003 A KR950028003 A KR 950028003A KR 1019940005953 A KR1019940005953 A KR 1019940005953A KR 19940005953 A KR19940005953 A KR 19940005953A KR 950028003 A KR950028003 A KR 950028003A
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KR
South Korea
Prior art keywords
conductive layer
semiconductor device
junction
circuit configuration
region
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Application number
KR1019940005953A
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Korean (ko)
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KR970006251B1 (en
Inventor
이충호
김홍범
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김광호
삼성전자 주식회사
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Priority to KR1019940005953A priority Critical patent/KR970006251B1/en
Publication of KR950028003A publication Critical patent/KR950028003A/en
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Publication of KR970006251B1 publication Critical patent/KR970006251B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체기판 상에 형성되고 그 하부에 얇은 절연막이 형성되어 있는 제1도전층; 상기 반도체기판의 일부 영역의 표면근방에 형성되고 두 개 이상의 PN접합을 가진 PN접합부; 상기 PN접합부의 소정영역과 상기 제1도전층을 연결하는 제2도전층; 및 상기 PN접합부의 다른 소정영역과 접속된 제3도전층을 구비하는 반도체장치를 제공한다.The present invention provides a semiconductor device comprising: a first conductive layer formed on a semiconductor substrate and having a thin insulating film formed thereon; A PN junction formed near a surface of a portion of the semiconductor substrate and having two or more PN junctions; A second conductive layer connecting the predetermined region of the PN junction and the first conductive layer; And a third conductive layer connected to another predetermined region of the PN junction portion.

PN접합부로 바이폴라 접합 트랜지스터가 형성되고, 제3도전층이 조절단자로 이용될 때, 플라즈마 공정 중 제1도전층 및 제2도전층에 유기되 이온들은, 상기 바이폴라 접합 트랜지스터를 통해 반도체기판으로 방전된다. 이는 얇은 절연막의 절연파괴를 방지하여 고신뢰도의 반도체소자를 얻을 수 있게 한다.When a bipolar junction transistor is formed with a PN junction and a third conductive layer is used as a control terminal, ions are induced in the first conductive layer and the second conductive layer during a plasma process, and ions are discharged to the semiconductor substrate through the bipolar junction transistor. do. This prevents breakdown of the thin insulating film, thereby making it possible to obtain a highly reliable semiconductor device.

Description

반도체 장치Semiconductor devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 전하측적에 의한 손상 감소를 위해 설계된 본 발명의 레이아웃도,4 is a layout diagram of the present invention designed to reduce damage by charge measurement,

제5도는 상기 제4도의 레이아웃도를 바탕으로 제조된 반도체장치의 단면도,FIG. 5 is a sectional view of a semiconductor device manufactured based on the layout diagram of FIG. 4;

제6도는 상기 제5도의 반도체장치를 간략하게 표시한 회로도.FIG. 6 is a circuit diagram schematically showing the semiconductor device of FIG.

Claims (12)

반도체기판 상에 형성되고 그 하부에 얇은 절연막이 형성되어 있는 제1도전층; 상기 반도체기판의 일부 영역의 표면근방에 형성되고 두 개 이상의 PN접합을 가진 PN접합을 가진 PN접합부; 상기 PN접합부의 소정영역과상기 제1도전층을 연결하는 제2도전층; 및 상기 PN접합부의 다른 소정영역과 접속된 제3도전층을 구비하는 것을 특징으로 하는 반도체장치.A first conductive layer formed on the semiconductor substrate and having a thin insulating film formed thereon; A PN junction portion formed near a surface of a portion of the semiconductor substrate and having a PN junction having two or more PN junctions; A second conductive layer connecting the predetermined region of the PN junction and the first conductive layer; And a third conductive layer connected to another predetermined region of the PN junction portion. 제1항에 있어서, 상기 얇은 절연막 하부에, 그 일부가 상기 반도체기판과 연결되어 있는 제4도전층을 더 구비하는 것을 특징으로 하는 반도체장치.2. The semiconductor device according to claim 1, further comprising a fourth conductive layer under the thin insulating film, the portion of which is connected to the semiconductor substrate. 제1항에 있어서, 상기 제3도전층은 상기 제2도전층 보다 면적이 작음을 특징으로 하는 반도체장치.The semiconductor device of claim 1, wherein the third conductive layer has a smaller area than the second conductive layer. 제1항에 있어서, 상기 PN접합부는 바이폴라 접합 트랜지스터 또는 SCR인 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein the PN junction is a bipolar junction transistor or an SCR. 제4항에 있어서, 상기 소정영역은 입력단자와 연결되는 불순물영역이고, 상기 다른 소정영역은 조절단자와 연결되는 불순물 영역인 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 4, wherein the predetermined region is an impurity region connected to an input terminal, and the other predetermined region is an impurity region connected to a control terminal. 제1항에 있어서, 상기 반도체기판의 일부 영역은, 회로구성상 필요한 소자가 형서되지 않는 여유영역인 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein the partial region of the semiconductor substrate is a spare region in which elements necessary for a circuit configuration are not formed. 제6항에 있어서, 상기 여유영역은, 소자분리영역 또는 칩과 칩사이의 스크라이브 영역인 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 6, wherein the spare area is an isolation region or a scribe area between the chip and the chip. 제1항에 있어서, 상기 제3도전층, 회로 구성 상 필요한 소자가 형성되지 않는 여유영역 전반에 걸쳐, 상기 회로구성 상 필요한 소자와는 전기적으로 절연되는 모양으로 형성된 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein the third conductive layer is formed so as to be electrically insulated from the elements required for the circuit configuration over the entire free area in which the elements necessary for the circuit configuration are not formed. 제1항에 있어서, 상기 제3도전층은, 상기 PN접합부 부근에서, 회로구성 상 필요한 소자와는 전기적으로 절연되는 모양으로 형성된 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein the third conductive layer is formed to be electrically insulated from a device necessary for a circuit configuration in the vicinity of the PN junction. 제1항에 있어서, 상기 제1도전층이 상부 도전층과 비아홀을 통해 연결될 때, 상기 제3도전층은 다른 비아홀을 통해, 상기 상부 도전층과 같은 층에 형성된 다른 상부 도전층과 연결되는 것을 특징으로 하는 반도체장치.The method of claim 1, wherein when the first conductive layer is connected to the upper conductive layer through the via hole, the third conductive layer is connected to another upper conductive layer formed in the same layer as the upper conductive layer through the other via hole. A semiconductor device characterized by the above-mentioned. 제10항에 있어서, 상기 다른 상부 도전층은, 회로구성 상 필요한 소자가 형성되지 않는 여유영역에서, 상기 회로구성 상 필요한 소자와는 전기적으로 절연되는 모양인 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 10, wherein the other upper conductive layer is electrically insulated from the elements necessary for the circuit configuration in a free region in which the elements necessary for the circuit configuration are not formed. 제10항에 있어서, 상기 상부 도전층 및 다른 상부 도전층은 단층 혹은 다층으로 형성된 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 10, wherein the upper conductive layer and the other upper conductive layer are formed in a single layer or multiple layers. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940005953A 1994-03-24 1994-03-24 Semiconductor device KR970006251B1 (en)

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Application Number Priority Date Filing Date Title
KR1019940005953A KR970006251B1 (en) 1994-03-24 1994-03-24 Semiconductor device

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Application Number Priority Date Filing Date Title
KR1019940005953A KR970006251B1 (en) 1994-03-24 1994-03-24 Semiconductor device

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Publication Number Publication Date
KR950028003A true KR950028003A (en) 1995-10-18
KR970006251B1 KR970006251B1 (en) 1997-04-25

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