KR950025985A - How to form a charge storage electrode - Google Patents

How to form a charge storage electrode Download PDF

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Publication number
KR950025985A
KR950025985A KR1019940003889A KR19940003889A KR950025985A KR 950025985 A KR950025985 A KR 950025985A KR 1019940003889 A KR1019940003889 A KR 1019940003889A KR 19940003889 A KR19940003889 A KR 19940003889A KR 950025985 A KR950025985 A KR 950025985A
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KR
South Korea
Prior art keywords
film
impurities
polysilicon film
forming
storage electrode
Prior art date
Application number
KR1019940003889A
Other languages
Korean (ko)
Inventor
임찬
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940003889A priority Critical patent/KR950025985A/en
Publication of KR950025985A publication Critical patent/KR950025985A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

반도체 소자의 캐패시터 용량을 극대화하는 반구형 전하저장전극 형성 방법에 관한 것으로 접촉하고 있는 도핑 돈반구형 폴리실리콘막(15)과 도핑되지 않은 폴리 실리콘막(16)을 질산용액 또는 인산용액으로 식각시 습식식각 선택비에 의해 도핑된 반구형 폴리 실리콘막(15)을 제거 시키고 도핑되지 않은 폴리 실리콘막(16)도 미소량이 식각되므로 요촐진 표면의 날카로움을 완화시켜 준다.The present invention relates to a method for forming a hemispherical charge storage electrode for maximizing the capacitor capacity of a semiconductor device. The doped hemispherical polysilicon film 15 is removed by the selectivity, and the undoped polysilicon film 16 also reduces the sharpness of the concave surface because a small amount is etched.

따라서 매우 높은 전장이 발생하는 전기장의 집중현상을 방지하여 전기적 특성을 개선하고 전하저장전극 형성의 효율성을 증대시킬수 있다.Therefore, it is possible to improve the electrical properties and increase the efficiency of charge storage electrode formation by preventing the concentration of the electric field that generates a very high electric field.

Description

전하 저장 전극 형성 방법How to form a charge storage electrode

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제6도는 본 발명에 따른 전하 저장 전극 제조 공정 단면도.6 is a cross-sectional view of a manufacturing process of a charge storage electrode according to the present invention.

Claims (3)

반도체기판 상에 필드 산화막(6)과 게이트 산화막(4') 게이트 전극(4), 소오스(10), 드레인(9) 및 트랜지스터 요소를 포함하는 구조를 갖는 웨이퍼 상에 전하저장 전극을 형성함에 있어서, 웨이퍼 전체구조 상부에 제1절연막(11, 11')과 제2절연막(14)을 차례로 형성하는 단계 ; 소오스 영역(10)상에 전하 저장 전극 콘택홀을 형성하고 이 콘택홀에 비정질 실리콘막(13)을 채우는 단계 ; 웨이퍼 전체 구조 상부에 상기 제2절연막(14)과 식각 선택비가 우수한 제3절연막(12)을 형성하는 단계 ; 마스크 및 식각 공정을 통해 상기 제3절연막(12)의 소정 부위를 식각하여 콘택부위의 비정질 실리콘 막(13)을 오픈(open)시키는 단계 ; 노출된 웨에퍼 전체 표면에 반구형 폴리 실리콘막(15)을 형성하는 단계 ; 반구형 폴리실리콘막(15)에 포클 도핑하여 불순물을 주입하는 단계 ; 웨이퍼 전체 구조 상부에 불순물이 도핑되지 않은 폴리 실리콘 막(16)을 적층한 후 상기 제3절연막(12)이 드러날 때 까지 에치 백(Each Back)하는 단계 ; 상기 제3절연막(12)을 식각하여 제거하는 단계 ; 상기 반구형 폴리 실리콘막(15)과 제2절연막(14)을 제거하는 단계 ; 상기 불순물이 주입되지 않은 폴리실리콘막(16)에 포클 도핑하여 전극으로서 역할을 하게 하는 단계를 포함하여 이루어 지는 것을 특징으로 하는 전하저장전극 형성방법.In forming a charge storage electrode on a wafer having a structure including a field oxide film 6, a gate oxide film 4 ', a gate electrode 4, a source 10, a drain 9, and a transistor element on a semiconductor substrate. Forming first insulating films 11 and 11 'and second insulating films 14 on the entire wafer structure; Forming a charge storage electrode contact hole on the source region 10 and filling the amorphous silicon film 13 in the contact hole; Forming a third insulating layer (12) having an excellent etching selectivity with the second insulating layer (14) on the entire wafer structure; Etching a predetermined portion of the third insulating layer 12 through a mask and an etching process to open the amorphous silicon layer 13 at the contact portion; Forming a hemispherical polysilicon film 15 on the entire surface of the exposed wafer; Injecting impurities into the hemispherical polysilicon film 15 by fockle doping; Stacking the polysilicon film 16 not doped with impurities on the entire structure of the wafer and etching back until the third insulating layer 12 is exposed; Etching and removing the third insulating layer 12; Removing the hemispherical polysilicon film 15 and the second insulating film 14; And foll doping the polysilicon layer (16) into which the impurities are not implanted to serve as an electrode. 제1항에 있어서, 상기 반구형 폴리 실리콘막(15)과 제2절연막(14)을 제거하는 단계는 불순물이 주입된 반구형 폴리실리콘(15)막과 불순물이 주입되지 않은 폴리 실리콘막(16)과의 습식식각 선택비가 우수한 용액을 사용하는 것을 특징으로 하는 전하 저장 전극 형성 방법.The method of claim 1, wherein the removing of the hemispherical polysilicon film 15 and the second insulating film 14 comprises a hemispherical polysilicon 15 film into which impurities are injected and a polysilicon film 16 into which impurities are not injected. A method of forming a charge storage electrode, comprising using a solution having an excellent wet etching selectivity. 제2항에 있어서, 불순물이 도핑된 반구형 폴리 실리콘막(15)과 불순물이 주입되지 않은 폴리 실리콘막(16)과의 습식식각비가 우수한 용액은 질산이 일정부분 포함된 용액인 것을 특징으로 하는 전하 저장 전극 형성 방법.3. The charge of claim 2, wherein the solution having excellent wet etching ratio between the hemispherical polysilicon film 15 doped with impurities and the polysilicon film 16 not implanted with impurities is a solution containing a portion of nitric acid. Storage electrode formation method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940003889A 1994-02-28 1994-02-28 How to form a charge storage electrode KR950025985A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100533378B1 (en) * 1999-07-02 2005-12-06 주식회사 하이닉스반도체 Method of forming vertical line of semiconductor device provided with plug-poly

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100533378B1 (en) * 1999-07-02 2005-12-06 주식회사 하이닉스반도체 Method of forming vertical line of semiconductor device provided with plug-poly

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