KR920010908A - DRAM cell having improved fin structure and manufacturing method thereof - Google Patents

DRAM cell having improved fin structure and manufacturing method thereof Download PDF

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Publication number
KR920010908A
KR920010908A KR1019900017705A KR900017705A KR920010908A KR 920010908 A KR920010908 A KR 920010908A KR 1019900017705 A KR1019900017705 A KR 1019900017705A KR 900017705 A KR900017705 A KR 900017705A KR 920010908 A KR920010908 A KR 920010908A
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KR
South Korea
Prior art keywords
poly
film
dram cell
fin structure
release
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Application number
KR1019900017705A
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Korean (ko)
Inventor
노병혁
강래구
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019900017705A priority Critical patent/KR920010908A/en
Priority to GB919100673A priority patent/GB9100673D0/en
Priority to DE4101939A priority patent/DE4101939A1/en
Priority to ITMI910132A priority patent/IT1245099B/en
Priority to JP3253023A priority patent/JPH079947B2/en
Publication of KR920010908A publication Critical patent/KR920010908A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

개선된 핀 구조를 갖는 디램 셀 및 그의 제조방법DRAM cell having improved fin structure and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 개선된 핀(fin) 구조를 갖는 디램 셀의 개략적 단면도, 제2도는 제1도의 A부분의 핀 구조의 부분 확대도.1 is a schematic cross-sectional view of a DRAM cell having an improved fin structure of the present invention, and FIG. 2 is a partial enlarged view of the fin structure of part A of FIG.

Claims (9)

반도체 기판(1)상에 필드 산화막(2), 게이트 폴리(3), 절연층(4) 및 액티브 영역(5)이 형성되어 있는 디램셀에 있어서, 상기 절연층(4)상에는 제1축적 폴리(7)가 콘택(6)을 통해 액티브 영역(5)과 직접 접촉되도록 형성되고, 상기 제1축적 폴리(7)와 제2축적 폴리(9) 및 제2축적 폴리 (9)와 제3축적 폴리(11) 사이에는 제1 및 제2이형물질(8), (10)이 각각 형성되며, 상기 축적 폴리(7),(9),(11)와 이형물질(8),(10)을 폴리(12), 유전체막(13) 및 플레이트 폴리(14)가 감싸도록 형성되는 것을 특징으로 하는 개선된 핀 구조를 갖는 디램 셀.In a DRAM cell in which a field oxide film 2, a gate poly 3, an insulating layer 4, and an active region 5 are formed on a semiconductor substrate 1, a first storage poly is formed on the insulating layer 4. (7) is formed in direct contact with the active region (5) via a contact (6), wherein the first and second accumulation polys (7) and (2) and (2) and (3) First and second release materials 8 and 10 are formed between the poly 11, respectively, and the accumulation polys 7, 9 and 11 and the release materials 8 and 10 are formed. A DRAM cell having an improved fin structure, wherein the poly 12, the dielectric film 13, and the plate poly 14 are formed to surround. 제1항에 있어서, 상기 이형물질(8), (10)이 상기 축적 폴리(7),(9) 및 (9),(11)간을 전기적으로 연결시켜 주기 위한 오믹콘택층의 기능과 지주기능을 하는 것을 특징으로 하는 개선된 핀 구조를 갖는 디램 셀의 제조방법.The function and support of the ohmic contact layer according to claim 1, wherein the release materials (8) and (10) electrically connect the accumulating polys (7), (9) and (9) and (11). A method of manufacturing a DRAM cell having an improved fin structure, characterized in that it functions. 제1항 또는 제2항에 있어서, 이형물질(8),(10)이 실리사이드막이나 도체 및 이들의 화합물인 것을 특징으로하는 개선된 핀 구조를 갖는 디램 셀.The DRAM cell of claim 1 or 2, wherein the release material (8), (10) is a silicide film, a conductor, or a compound thereof. 제1항에 있어서, 제1내지 제4축적 폴리(7),(9),(11)는 N형 불순물이 도우핑된 폴리실리콘막인 것을 특징으로하는 개선된 핀 구조를 갖는 디램 셀.The DRAM cell of claim 1, wherein the first to fourth storage poly (7), (9), and (11) are polysilicon films doped with N-type impurities. 반도체 기판(1)상에 필드 산화막(2), 게이트폴리(3), 절연막(4)과 액티브 영역(5)을 형성한 후 캐패시터를 형성하는 디램 셀의 제조방법에 있어서, 상기 절연막(4)을 식각하여 콘택(6)을 형성한 다음 폴리실리콘막을 침적시키고 N형 불순물을 이온주입하여 제1축적 폴리(7)를 형성하는 제1공정과, 제1축적 폴리(7) 상에 제1이형물질(8)을 형성하는 제2공정과, 폴리실리콘막을 침적시키고, N형 불순물을 이온주입하여 제2축적 폴리(9)를 형성하는 제3공정과, 제2축적 폴리(9) 상에 제2이형물질(10)을 형성하는 제4공정과, 폴리실리콘막을 침적시키고 N형 불순물을 이온주입하여 제3축적 폴리(11)를 형성하는 제5공정과, 상기 이형물질(8), (10)과 축적 폴리(7), (9),(11)을 패터닝하여 캐패시터의 패턴을 형성하는 제6공정과,이형물질(8),(10)을 다시 식각시키는 제7공정과, 폴리실리콘막을 얇게 침적시켜 상기 식각에 의해노출된이형물질(8),(10)을 감싸주기 위한 폴리(12)를 형성한 제8공정과, 캐패시터 유전체막(13)를 형성하는 제9공정과, 폴리실리콘막을 침적시켜 플레이트 전극(14)을 형성하는 제10공정을 구비하여 이루어지는 것을 특징으로 하는 개선된 핀 구조를 갖는 디램 셀의 제조방법.In the method for manufacturing a DRAM cell in which a field oxide film 2, a gate poly 3, an insulating film 4, and an active region 5 are formed on a semiconductor substrate 1, and then a capacitor is formed, the insulating film 4 Etching to form a contact 6, and then depositing a polysilicon film and implanting N-type impurities to form a first storage poly (7), and a first release on the first storage poly (7) A second step of forming the material (8), a third step of depositing a polysilicon film and ion implantation of N-type impurities to form the second storage poly (9), and the second storage poly (9) on the second storage poly (9). A fourth step of forming the second release material 10, a fifth step of depositing a polysilicon film and implanting N-type impurities to form a third storage poly 11, and the release material 8, 10 ) And the accumulating poly (7), (9), (11) to form a pattern of a capacitor, a sixth step of etching the release material (8), (10) again, and a polysilicon An eighth process of forming a poly 12 to cover the release materials 8 and 10 exposed by the etching by thinly depositing the lycon film, a ninth process of forming the capacitor dielectric film 13, And a tenth step of depositing a polysilicon film to form a plate electrode (14). 제5항에 있어서, 캐패시터의 유전체막(13)은 폴리(12)을 산화시켜 형성하는 것을 특징으로 하는 개선된 핀구조를 갖는 디램 셀의 제조방법.6. A method according to claim 5, wherein the dielectric film (13) of the capacitor is formed by oxidizing poly (12). 제5항에 있어서, 유전체막(13)으로 상기 폴리(12)를 산화시켜 산화막을 형성하고, 그위에 절연막과 산화막을 순차 형성한 ONO절연막을 사용하는 것을 특징으로 하는 개선된 핀 구조를 갖는 디램 셀의 제조방법.The DRAM having an improved fin structure according to claim 5, wherein an oxide film is formed by oxidizing the poly 12 with a dielectric film 13, and an ONO insulating film formed by sequentially forming an insulating film and an oxide film thereon is used. Method for producing a cell. 제5항에 있어서, 제7공정에서 폴리실리콘막(7),(9),(11)보다 식각 선택비가 큰 물질을 사용하여이형물질(8),(10)을 과다 식각하는 것을 특징으로 하는 개선된 핀 구조를 갖는 디램 셀의 제조방법.The method according to claim 5, wherein in the seventh step, the release material (8), (10) is overetched using a material having a larger etching selectivity than the polysilicon films (7), (9), and (11). A method of manufacturing a DRAM cell having an improved fin structure. 제5항에 있어서, 플레이트 전극(14)이 과다식각에 의해 이형물질이 식각된 축적 폴리(7),(9) 및 (9),(11)사이를 채워주는 것을 특징으로 하는 개선된 핀 구조를 갖는 디램 셀의 제조방법.6. The improved fin structure of claim 5, wherein the plate electrode 14 fills in between the accumulating polys (7), (9) and (9), (11) where the release material is etched by overetching. Method of manufacturing a DRAM cell having a. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900017705A 1990-11-01 1990-11-01 DRAM cell having improved fin structure and manufacturing method thereof KR920010908A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019900017705A KR920010908A (en) 1990-11-01 1990-11-01 DRAM cell having improved fin structure and manufacturing method thereof
GB919100673A GB9100673D0 (en) 1990-11-01 1991-01-11 Dram cell
DE4101939A DE4101939A1 (en) 1990-11-01 1991-01-21 Dynamic random-access memory cell - has memory layers in fin structure supported by intermediate heterogeneous layers
ITMI910132A IT1245099B (en) 1990-11-01 1991-01-22 DRAM CELL HAVING A PERFECTED FIN STRUCTURE AND ITS TRAINING PROCEDURE
JP3253023A JPH079947B2 (en) 1990-11-01 1991-09-04 Dynamic random access memory cell having improved fin structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900017705A KR920010908A (en) 1990-11-01 1990-11-01 DRAM cell having improved fin structure and manufacturing method thereof

Publications (1)

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KR920010908A true KR920010908A (en) 1992-06-27

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KR1019900017705A KR920010908A (en) 1990-11-01 1990-11-01 DRAM cell having improved fin structure and manufacturing method thereof

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JP (1) JPH079947B2 (en)
KR (1) KR920010908A (en)
DE (1) DE4101939A1 (en)
GB (1) GB9100673D0 (en)
IT (1) IT1245099B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19842684C1 (en) * 1998-09-17 1999-11-04 Siemens Ag Integrated circuit high-permittivity capacitor arranged on support structure in semiconductor arrangement e.g. for DRAM circuit or ADC

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0750347B1 (en) * 1987-06-17 2002-05-08 Fujitsu Limited Dynamic random access memory device and method of producing the same

Also Published As

Publication number Publication date
JPH0629479A (en) 1994-02-04
ITMI910132A0 (en) 1991-01-22
GB9100673D0 (en) 1991-02-27
DE4101939A1 (en) 1992-05-14
IT1245099B (en) 1994-09-13
ITMI910132A1 (en) 1992-05-02
JPH079947B2 (en) 1995-02-01

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