KR950025528A - Full adder - Google Patents

Full adder Download PDF

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Publication number
KR950025528A
KR950025528A KR1019940003767A KR19940003767A KR950025528A KR 950025528 A KR950025528 A KR 950025528A KR 1019940003767 A KR1019940003767 A KR 1019940003767A KR 19940003767 A KR19940003767 A KR 19940003767A KR 950025528 A KR950025528 A KR 950025528A
Authority
KR
South Korea
Prior art keywords
input
sum
connection node
transistor
inverted signal
Prior art date
Application number
KR1019940003767A
Other languages
Korean (ko)
Other versions
KR0146237B1 (en
Inventor
백종빈
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940003767A priority Critical patent/KR0146237B1/en
Publication of KR950025528A publication Critical patent/KR950025528A/en
Application granted granted Critical
Publication of KR0146237B1 publication Critical patent/KR0146237B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

본 발명은 캐리 발생부와 합 발생부를 독립적으로 구성함으로써, 캐리 및 함의 시간 지연을 줄여 동작 속도를 향상시키고 회로를 간단히 구성하여 래이아웃시에 차지하는 면적을 감소시킨 전 가산기에 관한 기술이다.The present invention relates to a total adder that independently configures a carry generation unit and a sum generation unit to reduce the carry and bin time delays to improve the operation speed, and to simply configure the circuit to reduce the area occupied during the layout.

Description

전 가산기Full adder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 전 가산기의 실시예를 도시한 회로도.2 is a circuit diagram showing an embodiment of the full adder of the present invention.

Claims (1)

세 신호를 입력으로 하여 그 합과 캐리를 구하기 위해 통상적인 캐리 발생부와 합 발생부를 포함하는 전 가산기에 있어서, 상기 합 발생부는, 제2입력과 접속노드 사이에 공통 접속되며 각각의 게이트는 제1입력과 제1입력의 반전신호에 의해 각각 제어되는 제1 PMOS형 트랜지스터 및 제1 NMOS형 트랜지스터와, 제1입력과 접속노드 및 제1입력의 반전신호와 접속노드를 각각 연결시키며 각각의 게이트는 제2입력에 의해 동시에 제어되는 제2 PMOS형 트랜지스터 및 제2 NMOS형 트랜지스터와, 접속노드와 합 출력을 연결하며 각각의 게이트는 제3입력 및 제3입력의 반전신호에 의해 각각 제어되는 제3PMOS형 트랜지스터 및 제3NMOS형 트랜지스터와, 제3입력과 합 출력 및 제3입력의 반전신호와 합 출력을 연결시키며 각각의 게이트는 접속노드에 의해 동시에 제어되는 제4 PMOS형 트랜지스터 및 제4 NMOS형 트랜지스터를 포함하는 것을 특징으로 하는 전가산기.In a full adder including a conventional carry generation section and a sum generation section for inputting three signals to obtain a sum and a carry, the sum generation section is commonly connected between the second input and the connection node, and each gate is formed of a first adder. A first PMOS transistor and a first NMOS transistor controlled by an inverted signal of a first input and a first input, and a first input and a connection node, and an inverted signal and a connection node of the first input, respectively, Is a second PMOS transistor and a second NMOS transistor that are simultaneously controlled by a second input, and a connection node and a sum output. Each gate is controlled by an inverted signal of the third input and the third input, respectively. The 3PMOS transistor and the 3NMOS transistor, and the third input, the sum output, and the inverted signal and the sum output of the third input are connected, and each gate is simultaneously controlled by the connection node. Fourth PMOS transistor and the fourth full adder comprises a NMOS transistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940003767A 1994-02-28 1994-02-28 Full adder KR0146237B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940003767A KR0146237B1 (en) 1994-02-28 1994-02-28 Full adder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940003767A KR0146237B1 (en) 1994-02-28 1994-02-28 Full adder

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1019970048868A Division KR0134038B1 (en) 1994-02-28 1997-09-25 Method for manufacturing balls of jointing sleeve

Publications (2)

Publication Number Publication Date
KR950025528A true KR950025528A (en) 1995-09-18
KR0146237B1 KR0146237B1 (en) 1998-09-15

Family

ID=19378017

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940003767A KR0146237B1 (en) 1994-02-28 1994-02-28 Full adder

Country Status (1)

Country Link
KR (1) KR0146237B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100476866B1 (en) * 1997-09-04 2005-08-29 삼성전자주식회사 Cmos full adder circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100521351B1 (en) * 1999-10-14 2005-10-12 삼성전자주식회사 Full adder

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100476866B1 (en) * 1997-09-04 2005-08-29 삼성전자주식회사 Cmos full adder circuit

Also Published As

Publication number Publication date
KR0146237B1 (en) 1998-09-15

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