KR950022422A - 64-bit block transfer controller between two buses with different data transfer arrangement positions - Google Patents

64-bit block transfer controller between two buses with different data transfer arrangement positions Download PDF

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Publication number
KR950022422A
KR950022422A KR1019930029346A KR930029346A KR950022422A KR 950022422 A KR950022422 A KR 950022422A KR 1019930029346 A KR1019930029346 A KR 1019930029346A KR 930029346 A KR930029346 A KR 930029346A KR 950022422 A KR950022422 A KR 950022422A
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South Korea
Prior art keywords
address
signal
bit block
data transfer
mblt
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KR1019930029346A
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Korean (ko)
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KR960009470B1 (en
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김병효
최동욱
임기욱
조호길
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양승택
재단법인 한국전자통신연구소
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

본 발명은 인털계열의 프로세서(팬티움)을 사용하는 시스템으로서 프로세서 버스와 VME64버스 사이의 데이타 전송 프로토콜의 차이를 극복하고, 64비트 블록 데이타 전송을 실현하기 위한 데이타 전송 배열위치가 상이한 두 버스사이의 64비트 블록전송 제어장치에 관한 것으로, 종래에 모토롤라 계열프로세서를 사용하는 버스 인터페이스로직에 비해 복잡한 로직에 의한 지연시간 증가로 성능저하의 문제점을 해결하기 위하여, 본 발명은 인털계열 프로세서(팬티움)를 VME64버스에 인터페이스시 제어신호의 비호환성과 데이타 포맷등의 불일치로 인하여 발생되는 변환로직의 복잡성과 이로인한 지연시간의 증가등과 같은 문제점을 VME64버스가 제어신호의 호환성이 있는 모토롤라 계열의 프로세서에 의해서 구동되었을 때와 같이 복잡하지 않는 약간의 로직을 추가하고, 또한 초기전송을 제외하고 가능한한 통신제어기의 제어신호를 이용하여 제어하므로서 적은 지연시간을 가지고 동작할 수 있는 VME64버스의 슬레이브 인터페이스를 설계함으로써 인터페이스 로직에 의해서 영향을 받지않고, 64비트 블록전송의 성능 향상을 할 수 있다.The present invention is a system using an inter-processor (Pantium) to overcome the differences in the data transfer protocol between the processor bus and the VME64 bus, and between two buses with different data transfer arrangement positions to realize 64-bit block data transfer. The present invention relates to a 64-bit block transmission control device of the present invention. In order to solve the problem of performance degradation due to increased delay time due to complicated logic, compared to a bus interface logic that uses a Motorola series processor, the present invention provides a processor for an intra system. ), The complexity of the conversion logic caused by incompatibility of control signal and inconsistency of data format when interfacing to VME64 bus. Some low complexity that is not as complex as when driven by a processor By designing the slave interface of the VME64 bus that can operate with a low delay time as well as control by using the control signal of the communication controller except the initial transmission, it is not affected by the interface logic and 64 bit. It can improve the performance of block transmission.

Description

데이터전송 배열위치가 상이한 두버스 사이의 64비트 블록전송 제어장치64-bit block transfer controller between two buses with different data transfer arrangement positions

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명이 적용대상으로 하는 인텔계열의 프로세서(팬티움)를 VME64 버스에 장착한 시스템의 구성도.1 is a configuration diagram of a system in which an Intel-based processor (Pantium) to which the present invention is applied is mounted on a VME64 bus.

제2도는 본 발명에 VME64 버스에 있는 통신제어기가 인텔계열의 프로세서(팬티움)버스의 자원을 64비트 블록전송에 의해서 억세스하는 방법을 설명하기 위한 도면FIG. 2 is a diagram for explaining a method in which a communication controller in a VME64 bus accesses resources of an Intel-based processor (pantomium) bus by 64-bit block transmission.

제3도는 본 발명의 64비트 블록전송 제어장치의 상세한 도면3 is a detailed diagram of a 64-bit block transmission control apparatus of the present invention.

제4도는 본 발명의 64비트 블록전송을 위해서, 입력로직들에 따라 제어신호를 발생하는데 필요한 알고리즘을 나타내는데 필요한 상태 천이도4 is a state transition diagram required to represent an algorithm required to generate a control signal according to input logics for 64-bit block transmission of the present invention.

제5도는 본 발명에 따른 동작흐름도5 is a flow chart according to the present invention

Claims (1)

VME64 버스(6, 21)내의 통신제어기(7)가 시스템 제어기(5)내의 자원을 억세스 64비트 블록 데이터의 전송을 제어하기 위하여 양방향 데이터 버퍼(8, 9, 10) 및 어드레스 버퍼(11)와, 64비트 블록전송을 위한 어드레스를 래치하기 위한 어드레스 카운터(12,13) 및 카운터 어드레스 버퍼(14, 15)로 구성된 데이터 전송경로와, write*, dbrdtack*, mblt* 또는 dbufen*의 신호를 해독하여 버퍼제어를 위한 신호(LVLE*, LVOE*, VLOE*, VLLE*)를 발생하기 위한 제3디코더(28)와, 상태제어기(22)에 dbrmreq*, dbrmgr*, ds* 또는 mblt* 신호들을 입력조건으로 하여 제어순서를 진행하고, 이 제어순서가 나타내는 상태를 이용하여 데이터의 읽기와 쓰기의 유효시점을 제어하기 위한 pds* 신호, 양방향 데이터 버퍼(14, 15)의 구동시점을 결정하기 위한 dbufen* 신호, 64비트 블록전송을 위해 초기 어드레스를 래치하기 위한 mblt-latchen* 신호, 다음 전송데이터의 위치를 나타내기 위해서 어드레스를 증가시키는 mblt-counten* 신호, 상기 어드레스 증가와 래치를 위한 인에이블 신호가 발생된 후 카운터(24, 26)의 클럭입력을 구동하기 위한 countclk 신호, 상기 어드레스가 래치되고나서 일정시간이 경과한 후 어드레스의 구동이 필요한 시점에 어드레스 카운터(24, 26)의 버퍼(25, 27)를 구동하기 위한 mblt-bufen* 신호를 발생시키기 위한 제2디코더(23)로 구성되는 데이터 전송 배열위치가 상이한 두 버스 사이의 64비트 블록전송 제어장치.The communication controller 7 in the VME64 buses 6 and 21 accesses the resources in the system controller 5 and the bidirectional data buffers 8, 9 and 10 and the address buffer 11 to control the transfer of 64-bit block data. A data transfer path comprising an address counter 12 and 13 and a counter address buffer 14 and 15 for latching an address for 64-bit block transfer, and a signal of write *, dbrdtack *, mblt * or dbufen * Third decoder 28 to generate signals for buffer control (LVLE *, LVOE *, VLOE *, VLLE *) and dbrmreq *, dbrmgr *, ds * or mblt * signals to the state controller 22. The control sequence is performed as an input condition, and the pds * signal for controlling the effective time of reading and writing data and the driving time of the bidirectional data buffers 14 and 15 are determined using the state indicated by this control sequence. dbufen * signal, latching initial address for 64-bit block transmission Mblt-latchen * signal for signal, mblt-counten * signal for increasing address to indicate the position of the next transmission data, enable signal for latch and address increase and then clock input of counters 24 and 26. A countclk signal for driving and an mblt-bufen * signal for driving the buffers 25 and 27 of the address counters 24 and 26 at a point in time when the address is required to be driven after a predetermined time has elapsed since the address is latched. A 64-bit block transfer control device between two buses having different data transfer arrangement positions, each having a second decoder (23). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR93029346A 1993-12-23 1993-12-23 64bit block transmission controller between buses with different data transmission array KR960009470B1 (en)

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Application Number Priority Date Filing Date Title
KR93029346A KR960009470B1 (en) 1993-12-23 1993-12-23 64bit block transmission controller between buses with different data transmission array

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KR950022422A true KR950022422A (en) 1995-07-28
KR960009470B1 KR960009470B1 (en) 1996-07-19

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