KR960009470B1 - 64bit block transmission controller between buses with different data transmission array - Google Patents

64bit block transmission controller between buses with different data transmission array Download PDF

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Publication number
KR960009470B1
KR960009470B1 KR93029346A KR930029346A KR960009470B1 KR 960009470 B1 KR960009470 B1 KR 960009470B1 KR 93029346 A KR93029346 A KR 93029346A KR 930029346 A KR930029346 A KR 930029346A KR 960009470 B1 KR960009470 B1 KR 960009470B1
Authority
KR
South Korea
Prior art keywords
address
buffers
driving
64bit
buses
Prior art date
Application number
KR93029346A
Other languages
Korean (ko)
Other versions
KR950022422A (en
Inventor
Byung-Hyo Kim
Dong-Wook Choe
Ki-Wook Lim
Ho-Kil Cho
Original Assignee
Korea Electronics Telecomm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Korea Electronics Telecomm filed Critical Korea Electronics Telecomm
Priority to KR93029346A priority Critical patent/KR960009470B1/en
Publication of KR950022422A publication Critical patent/KR950022422A/en
Application granted granted Critical
Publication of KR960009470B1 publication Critical patent/KR960009470B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

The controller includes a data transmission path consisting of bidirectional data buffers(8,9,10) and address buffer(11), and address counters(12,13) and counter address buffers(14,15), a third decoder(28) for generating signals for controlling the buffers, and a second decoder(23) for generating signals for controlling the effective time point of data reading and writing, determining the driving point of the bidirectional data buffers(14,15), latching the initial address, increasing the address, driving clock input of counters(24,26), and driving buffers(25,27) of the address counters(24,26) when an address driving is required.
KR93029346A 1993-12-23 1993-12-23 64bit block transmission controller between buses with different data transmission array KR960009470B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93029346A KR960009470B1 (en) 1993-12-23 1993-12-23 64bit block transmission controller between buses with different data transmission array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93029346A KR960009470B1 (en) 1993-12-23 1993-12-23 64bit block transmission controller between buses with different data transmission array

Publications (2)

Publication Number Publication Date
KR950022422A KR950022422A (en) 1995-07-28
KR960009470B1 true KR960009470B1 (en) 1996-07-19

Family

ID=19372394

Family Applications (1)

Application Number Title Priority Date Filing Date
KR93029346A KR960009470B1 (en) 1993-12-23 1993-12-23 64bit block transmission controller between buses with different data transmission array

Country Status (1)

Country Link
KR (1) KR960009470B1 (en)

Also Published As

Publication number Publication date
KR950022422A (en) 1995-07-28

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