KR950021126A - Metal wiring layer formation method - Google Patents

Metal wiring layer formation method Download PDF

Info

Publication number
KR950021126A
KR950021126A KR1019930031843A KR930031843A KR950021126A KR 950021126 A KR950021126 A KR 950021126A KR 1019930031843 A KR1019930031843 A KR 1019930031843A KR 930031843 A KR930031843 A KR 930031843A KR 950021126 A KR950021126 A KR 950021126A
Authority
KR
South Korea
Prior art keywords
forming
line region
pattern
reflectance
reflection film
Prior art date
Application number
KR1019930031843A
Other languages
Korean (ko)
Other versions
KR0122524B1 (en
Inventor
함영목
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930031843A priority Critical patent/KR0122524B1/en
Publication of KR950021126A publication Critical patent/KR950021126A/en
Application granted granted Critical
Publication of KR0122524B1 publication Critical patent/KR0122524B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 금속배선층 형성방법에 관한 것으로, 공지의 기술로 실리콘기판 상부에 하부층, 금속층 및 반사방지막을 증착하고 단차가 낮은 스프레핑라인지역의 반사방지막을 식각함으로써, 셀지역과 스프레핑라인 지역에 미세패턴을 형성할 수 있는 균일도가 높은 감광막패턴을 형성하여 반도체소자의 수율을 향상시키는 기술이다.The present invention relates to a method for forming a metal wiring layer, by depositing a lower layer, a metal layer and an anti-reflection film on a silicon substrate by a known technique, and etching the anti-reflection film in the low-spreading line region by etching a step, to the cell region and the spreading line region It is a technology for improving the yield of a semiconductor device by forming a photosensitive film pattern having a high uniformity capable of forming a fine pattern.

Description

금속배선층 형성방법Metal wiring layer formation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2a도 내지 제2c도는 본 발명의 실시예에 의한 금속배선층 형성공정을 도시한 단면도.2a to 2c are cross-sectional views showing a metal wiring layer forming process according to an embodiment of the present invention.

Claims (4)

실리콘기판의 상부에 공지의 기술로 하부층을 형성하고 그 상부에 금속층과 반사방지막을 증착하는 공정과, 상기 반사방지막의 상부에 감광막을 도포한 후, 스트레핑라인지역의 감광막을 노광, 현상함으로써 감광막패턴을 형성하고 상기 감광막패턴을 마스크로 하여 반사방지막을 식각한후, 상기 감광막패턴을 제거하여 반사방지막패턴을 형성하는 공정과, 전체구조상부에 공지의 기술로 미세패턴을 형성하기 위한 균일도가 높은 감광막패턴을 형성하는 공정을 포함하는 금속배선층 형성방법.Forming a lower layer on the silicon substrate by a known technique, depositing a metal layer and an antireflection film on the upper surface of the silicon substrate; Forming a pattern, etching the anti-reflection film using the photoresist pattern as a mask, and then removing the photoresist pattern to form an anti-reflection film pattern, and having high uniformity for forming a fine pattern on the entire structure by a known technique. A metal wiring layer forming method comprising the step of forming a photosensitive film pattern. 제1항에 있어서, 상기 반사방지막패턴은 스트레핑라인지역의 반사율을 높여 균일도가 높은 미세패턴을 형성하기 위하여 형성한 것을 특징으로 하는 금속배선층 형성방법.The method of claim 1, wherein the anti-reflection film pattern is formed to form a fine pattern with high uniformity by increasing the reflectance of the strapping line region. 제2항에 있어서, 상기 스트레핑라인지역의 반사율을 높이기 위하여 상기 금속층으로 사용되는 알루미늄층의 스트레핑라인지역을 부분식각하는 것을 특징으로 하는 금속배선층 형성방법.3. The method of claim 2, wherein the stripping line region of the aluminum layer used as the metal layer is partially etched to increase the reflectance of the stripping line region. 제2항에 있어서, 상기 스트레핑라인지역의 반사율을 높이기 위하여 고반사율의 금속을 스트레핑라인 지역에 증착하는 것을 특징으로 하는 금속배선층 형성방법.3. The method of claim 2, wherein a metal having a high reflectance is deposited in the strapping line region in order to increase the reflectance of the strapping line region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930031843A 1993-12-31 1993-12-31 Formation method of metal wiring layer KR0122524B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930031843A KR0122524B1 (en) 1993-12-31 1993-12-31 Formation method of metal wiring layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930031843A KR0122524B1 (en) 1993-12-31 1993-12-31 Formation method of metal wiring layer

Publications (2)

Publication Number Publication Date
KR950021126A true KR950021126A (en) 1995-07-26
KR0122524B1 KR0122524B1 (en) 1997-11-26

Family

ID=19374777

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930031843A KR0122524B1 (en) 1993-12-31 1993-12-31 Formation method of metal wiring layer

Country Status (1)

Country Link
KR (1) KR0122524B1 (en)

Also Published As

Publication number Publication date
KR0122524B1 (en) 1997-11-26

Similar Documents

Publication Publication Date Title
KR970003459A (en) Method of forming via hole in semiconductor device
KR960035802A (en) Fine pattern formation method and metal wiring formation method using the same
KR950021126A (en) Metal wiring layer formation method
KR100826964B1 (en) Method for fabricating semiconductor device
KR940002956A (en) Metal wiring formation method
KR970077196A (en) METHOD FOR FORMING METAL WIRING IN SEMICONDUCTOR
KR100248345B1 (en) Method of forming metal interconnector in semiconductor device
KR0144140B1 (en) Metal wiring method
KR970053509A (en) Method of forming multiple metal layers in semiconductor devices
KR970018126A (en) How to form a fine pattern
KR960002675A (en) Metal pattern formation method
KR930024106A (en) Contact Forming Method of Semiconductor Device
KR960002575A (en) Metal wiring formation method of semiconductor device
KR940016508A (en) Method for manufacturing a contact of a semiconductor device having an inclined surface
KR980003891A (en) Manufacturing method of alignment key for exposure
KR960005813A (en) Manufacturing method of semiconductor device
KR940022702A (en) Metal wiring formation method of semiconductor device
KR970053021A (en) Method of forming a semiconductor device
KR970018180A (en) Semiconductor device manufacturing method
KR970018032A (en) Small contact formation method of semiconductor device
KR960026303A (en) Fine pattern formation method
KR970072140A (en) Pattern formation method of semiconductor device
KR940002957A (en) Photosensitive film pattern formation method
KR970018409A (en) Metal wiring formation method of semiconductor device
KR970018198A (en) Planarization method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100825

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee