KR950020120A - Data Buffer Enable Circuit - Google Patents

Data Buffer Enable Circuit Download PDF

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Publication number
KR950020120A
KR950020120A KR1019930026420A KR930026420A KR950020120A KR 950020120 A KR950020120 A KR 950020120A KR 1019930026420 A KR1019930026420 A KR 1019930026420A KR 930026420 A KR930026420 A KR 930026420A KR 950020120 A KR950020120 A KR 950020120A
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KR
South Korea
Prior art keywords
data
data buffer
board
enable
address
Prior art date
Application number
KR1019930026420A
Other languages
Korean (ko)
Other versions
KR950014995B1 (en
Inventor
김진호
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019930026420A priority Critical patent/KR950014995B1/en
Publication of KR950020120A publication Critical patent/KR950020120A/en
Application granted granted Critical
Publication of KR950014995B1 publication Critical patent/KR950014995B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

본 발명은 동일 데이타/어드레스 버스 라인을 통하여 여러장의 보오드에 데이타 코오드와 어드레스 코오드를 인가시키는 시스템에 있어서, 보오드의 변경, 추가 삭제가 용이하도록 데이타 버퍼를 각 보오드로 부터 생성되는 트리 스테이트 출력의 보오드 데이타 인에이블 신호로 인에이블 시킬 수 있도록 한 데이타 버퍼 인에이블 회로에 관한 것이다. 종래의 데이타 버퍼 인에이블 회로는 제1도에서와 같이 각 보오드(30)(60)에 구성되어진 데이타 버퍼(40)(70)를 인에이블 시키는 어드레스 데코우더(50)(80)와 데이타 버퍼(20)를 인에이블 시키는 데이타 버퍼 인에이블 회로(90)가 별도로 구성되어져 시스템을 변경, 추가, 삭제가 용이하지 못했다. 따라서 본 발명은 제2도에서와 같이 각 보오드(30)(60)의 어드레스 데코우더(50)(80)로 부터 데이타 버퍼(40)(70)에 인에이블 신호가 유입되는 트리 스테이트 출력을 와이어 엔드(Wire And) 결합시켜 데이타 버퍼(20)에 인가되도록 구성한 것이다.According to the present invention, in a system for applying a data code and an address code to multiple boards through the same data / address bus line, a board of a tree state output in which data buffers are generated from each board so as to easily change or add or delete boards. The present invention relates to a data buffer enable circuit capable of enabling a data enable signal. Conventional data buffer enable circuits include address decoders 50 and 80 and data buffers that enable data buffers 40 and 70 configured in each board 30 and 60 as shown in FIG. The data buffer enable circuit 90 for enabling 20) is configured separately, so that it is not easy to change, add, or delete the system. Accordingly, the present invention wires the tree state outputs to which enable signals flow from the address decoders 50 and 80 of the respective boards 30 and 60 to the data buffers 40 and 70 as shown in FIG. It is configured to be applied to the data buffer 20 by combining end (Wire And).

Description

데이타 버퍼 인에이블 회로Data Buffer Enable Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래 발명에 대한 블록도,1 is a block diagram of a conventional invention,

제2도는 본 발명에 따른 블록도이다.2 is a block diagram according to the present invention.

Claims (1)

CPU(10)로 부터 출력된 데이타 코오드를 데이타 버퍼(20)를 통하여 각 보오드(30)(60)에 구성된 데이타 버퍼(40)(70)에 인가시키는 한편 어드레스 코오드를 어드레스 버스를 통하여 각 보오드(30)(60)에 구성된 어드레스 데코우더(50)(80)에 인가시켜 각 보오드(30)의 데이타 버퍼(40)(70)를 인에이블 시키는 시스템에 있어서, 각 보오드(30)(60)의 어드레스 데코우더(50)(80)르 부터 데이터 버퍼(40)(70)에 인에이블 신호가 유입되는 트리스테이트 출력을 와이어 엔드(Wire And)결합시켜 데이타 버퍼(20)에 인가시키도록 구성되어진 특징을 갖는 데이터 버퍼인에이블 회로.The data code output from the CPU 10 is applied to the data buffers 40 and 70 configured in each board 30 and 60 through the data buffer 20 while the address code is applied to each board through the address bus. In the system which applies to the address decoders 50 and 80 configured in the 30 and 60 to enable the data buffers 40 and 70 of each board 30, It is configured to apply a wire state to the data buffer 20 by a wire end coupling of the tristate output from which the enable signal flows from the address decoders 50 and 80 to the data buffers 40 and 70. A data buffer enable circuit having: ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930026420A 1993-12-03 1993-12-03 Data buffer enable circuit KR950014995B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930026420A KR950014995B1 (en) 1993-12-03 1993-12-03 Data buffer enable circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930026420A KR950014995B1 (en) 1993-12-03 1993-12-03 Data buffer enable circuit

Publications (2)

Publication Number Publication Date
KR950020120A true KR950020120A (en) 1995-07-24
KR950014995B1 KR950014995B1 (en) 1995-12-21

Family

ID=19369860

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930026420A KR950014995B1 (en) 1993-12-03 1993-12-03 Data buffer enable circuit

Country Status (1)

Country Link
KR (1) KR950014995B1 (en)

Also Published As

Publication number Publication date
KR950014995B1 (en) 1995-12-21

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