KR950015750A - Reference voltage generation circuit of semiconductor integrated device - Google Patents

Reference voltage generation circuit of semiconductor integrated device Download PDF

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Publication number
KR950015750A
KR950015750A KR1019930025325A KR930025325A KR950015750A KR 950015750 A KR950015750 A KR 950015750A KR 1019930025325 A KR1019930025325 A KR 1019930025325A KR 930025325 A KR930025325 A KR 930025325A KR 950015750 A KR950015750 A KR 950015750A
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South Korea
Prior art keywords
voltage
reference voltage
power supply
generating
boosted
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KR1019930025325A
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Korean (ko)
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KR0153542B1 (en
Inventor
임영호
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김광호
삼성전자 주식회사
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Priority to KR1019930025325A priority Critical patent/KR0153542B1/en
Priority to US08/348,183 priority patent/US5619124A/en
Priority to JP6293511A priority patent/JPH07194099A/en
Publication of KR950015750A publication Critical patent/KR950015750A/en
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Publication of KR0153542B1 publication Critical patent/KR0153542B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Electromagnetism (AREA)
  • Automation & Control Theory (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Control Of Electrical Variables (AREA)
  • Dram (AREA)
  • Dc-Dc Converters (AREA)

Abstract

본 발명은 외부에서 입력되는 전원전압을 입력하여 일정한 전압 레벨을 가지는 기준전압을 발생하기 위한 기준전압 발생회로에 있어서, 상기 전원전압 레벨 이상으로 승압된 승압전압을 발생하기 위한 고전압 발생수단과, 상기 승압전압을 일정 전압 이하로 클램프하기 위한 클램핑 수단과, 상기 클램핑 수단을 통하여 클램프된 상기 승압전압의 리플을 방지하기 위한 리플 방지 수단과, 상기 리플 방지 수단을 통하여 출력되는 상기 승압전압을 감압하여 상기 전원전압 레벨 이하의 기준전압을 출력하기 위한 전압 분할 수단을 구비함을 특징으로 한다. 본 발명에 의한 기준전압 발생회로에 의하여 외부에서 입력되는 전원전압의 변화, 반도체 집적 장치의 제조 공정 및 온도 편차에 따른 변화에 무관하게 일정한 전압 레벨을 가지는 기준전압을 제공함으로서 전체적인 반도체 집적회로의 동작 안정성 및 신뢰성이 향상되는 효과가 있다.The present invention provides a reference voltage generating circuit for generating a reference voltage having a constant voltage level by inputting a power supply voltage input from an external device, comprising: high voltage generating means for generating a boosted voltage stepped up above the power supply voltage level; Clamping means for clamping the boosted voltage below a predetermined voltage, ripple preventing means for preventing ripple of the boosted voltage clamped through the clamping means, and depressurizing the boosted voltage outputted through the ripple preventing means And voltage dividing means for outputting a reference voltage below the power supply voltage level. Operation of the overall semiconductor integrated circuit by providing a reference voltage having a constant voltage level regardless of the change in the power supply voltage input from the outside by the reference voltage generating circuit according to the present invention, the manufacturing process of the semiconductor integrated device and the change due to temperature variation Stability and reliability are improved.

Description

반도체 집적장치의 기준전압 발생회로Reference voltage generation circuit of semiconductor integrated device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제7도는 본 발명에 의한 기준전압 발생회로의 블럭 다이어그램을 보이는 도면,7 is a block diagram of a reference voltage generation circuit according to the present invention;

제8도는 제7도에 따른 기준전압 발생회로의 상세 회로를 보이는 도면,8 is a view showing a detailed circuit of the reference voltage generation circuit according to FIG.

제9도는 제8도에 따른 기준전압 발생회로의 동작 타이밍도를 보이는 도면.9 is a view showing an operation timing diagram of a reference voltage generation circuit according to FIG. 8;

Claims (13)

외부에서 입력되는 전원전압을 입력하여 일정한 전압 레벨을 가지는 기준전압을 발생하기 위한 기준전압 발생회로에 있어서, 상기 전원전압 레벨 이상으로 승압된 승압전압을 발생하기 위한 고전압 발생수단과, 상기 승압전압을 일정 전압 이하로 클램프하기 위한 클램핑 수단과, 상기 클램핑 수단을 통하여 클램프된 상기 승압전압의 리플을 방지하기 위한 리플 방지 수단과, 상기 리플 방지 수단을 통하여 출력되는 상기 승압전압을 감압하여 상기 전원전압 레벨 이하의 기준전압을 출력하기 위한 전압 분할 수단을 구비함을 특징으로 하는 기준전압 발생회로.A reference voltage generating circuit for generating a reference voltage having a constant voltage level by inputting a power supply voltage input from an external device, the reference voltage generating circuit comprising: high voltage generating means for generating a boosted voltage stepped up above the power supply voltage level and the boosted voltage; Clamping means for clamping below a predetermined voltage, ripple preventing means for preventing ripple of the boosted voltage clamped through the clamping means, and reducing the boost voltage output through the ripple preventing means to reduce the power supply voltage level. And a voltage dividing means for outputting the following reference voltages. 제1항에 있어서, 상기 고전압발생수단은 소정의 펌핑 클럭에 대응되어 상기 전원전압을 승압하기 위한 차아지 펌핑 캐패시터로 이루어짐을 특징으로 하는 기준전압 발생회로.The reference voltage generating circuit according to claim 1, wherein the high voltage generating means comprises a charge pumping capacitor for boosting the power supply voltage in response to a predetermined pumping clock. 제1항에 있어서, 상기 클램핑 수단은 소정의 역방향브레이크 다운 전압에 의하여 상기 승압전압이 클램프 록 다이오드로 이루어짐을 특징으로 하는 기준전압 발생회로.The reference voltage generating circuit according to claim 1, wherein the clamping means comprises a clamp lock diode in which the boost voltage is applied by a predetermined reverse break down voltage. 제1항에 있어서, 상기 리플 방지 수단은 소정의 캐패시턴스를 가지는 쾌패시티르 이루어짐을 특징으로 하는 기준전압 발생회로.The reference voltage generating circuit according to claim 1, wherein the ripple preventing means is made of a high capacitance having a predetermined capacitance. 제1항에 있어서, 클램프된 상기 승압전압은 1OV-18V임을 특징으로 하는 기준전압 발생회로.The reference voltage generator of claim 1, wherein the boosted voltage is 1OV-18V. 제1항에 있어서, 상기 기준전압은 1V-3V임을 특징으로 하는 기준전압 발생회로.The reference voltage generator of claim 1, wherein the reference voltage is 1V-3V. 제1항에 있어서, 상기 전압분할 회로는 두개의 직렬연결된 저항소자로 이루어짐을 특징으로하는 기준전압 발생회로.The reference voltage generator of claim 1, wherein the voltage division circuit comprises two series connected resistance elements. 제7항에 있어서, 상기 저항소자는 폴리실리콘 저항 또는 불순물 확산 저항으로 이루어짐을 특징으로 하는 기준전압 발생회로.8. The reference voltage generating circuit according to claim 7, wherein the resistance element is made of polysilicon resistance or impurity diffusion resistance. 외부에서 입력되는 전원전압을 입력하여 일정한 전압 레벨을 가지는 기준전압을 발생하기 위한 기준전압 발생회로에 있어서, 상기 전원전압 레벨 이상으로 승압된 승압전압을 발생하기 위한 고전압 발생수단과, 상기 승압전압을 일정 전압 이하로 클램프하기 위한 클램핑 수단과, 상기 승압전압을 입력하여 상기 전원전압 레벨 이하의 기준전압이 출력되도록 상기 승압전압을 감압하는 전압분할 수단을 구비함을 특징으로 하는 반도체 집적회로.A reference voltage generating circuit for generating a reference voltage having a constant voltage level by inputting a power supply voltage input from an external device, the reference voltage generating circuit comprising: high voltage generating means for generating a boosted voltage stepped up above the power supply voltage level and the boosted voltage; And clamping means for clamping below a predetermined voltage, and voltage dividing means for reducing the boosted voltage to input a boosted voltage to output a reference voltage below the power supply voltage level. 제9항에 있어서, 상기 고전압 발생수단은 소정의 펌핑 클럭에 대응되어 상기 전원전압을 승아하기 위한 차아지 펌핑 캐패시터로 이루어짐을 특징으로 하는 반도체 집적 회로.10. The semiconductor integrated circuit according to claim 9, wherein said high voltage generating means comprises a charge pumping capacitor for boosting said power supply voltage in response to a predetermined pumping clock. 제9항에 있어서, 상기 전압 분할 회로는 직렬 연결된 저항소자로 이루어짐을 특징으로 하는 반도체 집적회로.The semiconductor integrated circuit of claim 9, wherein the voltage dividing circuit is formed of a resistor connected in series. 제9항에 있어서, 상기 승압전압은 1OV-18V임을 특징으로 하는 반도체 집적 회로.10. The semiconductor integrated circuit according to claim 9, wherein the boost voltage is 1OV-18V. 제9항에 있어서, 상기 기준전압은 1V-3V임을 특징으로 하는 반도체 집적 회로.The semiconductor integrated circuit of claim 9, wherein the reference voltage is 1V-3V. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930025325A 1993-11-26 1993-11-26 Reference voltage generating circuit KR0153542B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019930025325A KR0153542B1 (en) 1993-11-26 1993-11-26 Reference voltage generating circuit
US08/348,183 US5619124A (en) 1993-11-26 1994-11-28 Reference voltage generator in a semiconductor integrated device
JP6293511A JPH07194099A (en) 1993-11-26 1994-11-28 Reference voltage generating circuit

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Application Number Priority Date Filing Date Title
KR1019930025325A KR0153542B1 (en) 1993-11-26 1993-11-26 Reference voltage generating circuit

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KR950015750A true KR950015750A (en) 1995-06-17
KR0153542B1 KR0153542B1 (en) 1998-10-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100813550B1 (en) * 2006-12-07 2008-03-17 주식회사 하이닉스반도체 Circuit for generating reference voltage of semiconductor memory apparatus

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2878986B1 (en) * 2004-12-08 2007-04-27 Atmel Corp PRINCIPLE OF POWER CONTROL OF HIGH VOLTAGE OUTPUT IN INTEGRATED CIRCUIT DEVICES
JP4837519B2 (en) * 2006-10-16 2011-12-14 株式会社 日立ディスプレイズ Display device drive circuit
KR101511762B1 (en) * 2008-07-01 2015-04-14 삼성전자주식회사 Circuit for generating reference voltage
JP5646360B2 (en) 2011-02-04 2014-12-24 株式会社東芝 Semiconductor device
US9158320B1 (en) * 2014-08-07 2015-10-13 Psikick, Inc. Methods and apparatus for low input voltage bandgap reference architecture and circuits
JP6657035B2 (en) * 2016-06-28 2020-03-04 エイブリック株式会社 Boost circuit
KR102553262B1 (en) * 2017-11-17 2023-07-07 삼성전자 주식회사 Reference voltage generator and memory device including the same
US10985653B1 (en) * 2020-03-20 2021-04-20 Infineon Technologies Ag Charge pump converter and control method

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JPH06104672A (en) * 1992-09-22 1994-04-15 Mitsubishi Electric Corp Clamp circuit
US5497119A (en) * 1994-06-01 1996-03-05 Intel Corporation High precision voltage regulation circuit for programming multilevel flash memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100813550B1 (en) * 2006-12-07 2008-03-17 주식회사 하이닉스반도체 Circuit for generating reference voltage of semiconductor memory apparatus

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US5619124A (en) 1997-04-08
KR0153542B1 (en) 1998-10-15
JPH07194099A (en) 1995-07-28

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