KR950013903B1 - Dram cell manufacturing process - Google Patents

Abstract

The method for manufacturing a high integrated DRAM cell comprises the steps of: forming a second conductivity type of first well over a first conductivity type of semiconductor substrate and forming a first conductivity type of second well in the first well; forming a trench type element separation insulating layer inside of the second well; sequentially forming a pad oxide layer and a nitride layer thereover and forming a first trench at a part of an active region; forming a first conductivity type of diffusion layer inside of the first trench; forming an oxide layer and forming a second trench at the lower portion of the first trench; doping the second conductivity type of impurity in the second trench and forming a lower plate electrode; forming a first dielectric layer and a first conductive layer, doping the photo resist and forming a first storage electrode; exposing the region which is to be a source diffusion layer and a trench region and then forming a second conductivity type of source diffusion layer; removing the photo resist and forming a second conductive layer thereover; removing the second conductive layer and nitride layer; removing the photo resist, polishing the second conductive layer, exposing the nitride layer and sequentially depositing a second dielectric layer and a third conductive layer thereover; polishing or etching back the third conductive layer and second dielectric layer to expose the nitride layer; and removing the remaining nitride layer and forming an upper plate electrode.

Description

Manufacturing method of high density DRAM cell

1A and 1B are cross-sectional views each showing a DRAM cell structure and a schematic circuit diagram constructed according to the present invention.

2A to 2O are cross-sectional views illustrating a method for manufacturing a DRAM cell according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a highly integrated DRAM cell that aims at increasing cell capacitance and improving planarization in a cell.

In the high density DRAM cell manufacturing method, the maximum capacitance in the small area of the cell should be obtained as the density of the memory cell is improved due to the reduction of data error due to external charge as much as possible. It should be easy to make the flattening is made to facilitate the metallization process.

In view of this, many conventional studies (see IEDM, pp328 ~ 331,1987) use a p ⁺ epitaxy layer using a plate as a lower plate electrode. The lower plate electrode used is simultaneously connected with the substrate bias of the access transistor to maintain the same potential at all times. In other words, when a negative voltage of several volts is applied to improve the characteristics of the access transistor, the same voltage is applied to the p ⁺ cell plate, thereby decreasing the reliability of the dielectric layer and increasing the depletion layer, thereby inevitably reducing the cell capacitance. In general, when 1/2 Vcc is applied to the plate electrode of the capacitor, a minimum electric field is applied to the dielectric film. Therefore, 1 / 2Vcc should be applied to the upper plate of the capacitor, and thus the potential is applied differently to the upper plate electrode and the lower plate electrode. Therefore, the capacitance is reduced because the lower dielectric layer and the upper dielectric layer must be thickly applied for safe cell operation. There is no way. In addition, when the gate electrode is formed at the patterned position of the first storage electrode, the overlap of the gate electrode may be unstable when the source and drain region diffusion layers are formed, thereby reducing the driving capability of the transistor.

Accordingly, an object of the present invention is to provide a method for fabricating a highly integrated DRAM cell using a triple well and a self-aligned gate electrode to improve the above problem.

To achieve the object of the present invention, an n-type well is formed in a p-type substrate and a p-type well is formed again in this n-type well. That is, a PNP type well (or vice versa NPN well) is formed to form a plate terminal of a substrate capacitor formed in the substrate in the n type well to be separated from the p type well which is the substrate of the access transistor. In this manner, a back bias is applied to the P-type wells to improve the characteristics of the access transistor, and each capacitor is applied to the n-type wells by applying a potential of 1/2 Vcc equal to the plate electrode of the second capacitor. Minimal electric field acts on the dielectric film to improve reliability, thereby maximizing the capacitance of the capacitor without having to increase the thickness of the capacitor dielectric film as a compensation for the high electric field.

According to the present invention, by forming an insulating film 5 times thicker than the gate dielectric film on the sidewall of the trench, it is possible to prevent leakage current of the n ⁺ layer, which is a plate electrode, in the n-type well from the source electrode of the transistor parasiticly generated by the storage electrode. do.

In addition, after exposing the storage electrode and the upper plate electrode to an activation region (a part of the channel region, the drain region, and the source region of the access transistor), the gate electrode is provided as a diffusion layer of the source and drain regions by self-alignment to form an access transistor. As a result, the overlap with the transistor electrode can be stabilized, thereby maximizing the driving capability of the transistor. That is, the present invention can improve the planarization which has been a problem in the highly integrated memory cell by forming a double plate capacitor using a triple well and a trench cell, and at the same time, can maximize the capacitance.

A method for manufacturing a DRAM cell as an embodiment of the present invention can be described as follows with the accompanying drawings.

FIG. 1A is a cross-sectional view of a DRAM cell structure constructed by the present invention, which is formed parasitic by the first storage electrode 25 by forming an oxide film 19 having a thickness of at least five times the gate dielectric film on the trench sidewalls. It can be seen that leakage current from the source 30 of the transistor to the n ⁺ layer 21 which is the plate electrode in the n-type well 6 can be prevented.

1B is a schematic circuit diagram of a DRAM cell according to the present invention. As shown in the figure, it can be seen that the lower capacitor C1 does not affect the substrate bias of the access transistor.

With reference to Figures 2a to 2o will be described a specific embodiment of the present invention.

2a shows a second conductivity type, i.e., an n-type well 3, formed on a first conductivity type, for example a p-type substrate 1, by a conventional method, and inside the n-type well 3; That is, the p-type well 7 is formed again to form a triple well structure as a whole, and then the oxide film 7 and the silicon nitride film 9 are sequentially deposited. In this case, the n-type well and p-type well is formed of an epitaxial layer or an ion implantation diffusion layer by a conventional process. Next, a trench forming process and a boron ion implantation process are performed to form a trench type device isolation insulating layer through a photolithography process on a front surface thereof.

Referring to FIG. 2B, a trench type isolation layer 11 is formed in the formed trench of FIG. 2A and the oxide and silicon nitride layers are etched.

Referring to FIG. 2C, after the pad oxide layer 13 is formed on the entire surface of the semiconductor substrate and the silicon nitride layer 15 is deposited again, a first trench is formed through a photolithography process. At this time, the depth of the first trench is formed deeper than the depth of the p-type well (5) and the level is about 1 ~ 2㎛. Subsequently, a p ⁺ diffusion layer 17 having a concentration of 10 ¹⁷ to 10 ¹⁹ # / cm 3 is formed on the side of the first trench to prevent leakage current between the source diffusion layer and the lower capacitor electrode induced by the storage electrode of the capacitor.

Referring to FIG. 2D, after the first trench is formed, an oxide film 19 for sidewall spacers of about 900 to 1,000 Å is deposited on the entire surface of the wafer.

Referring to FIG. 2E, a second trench is formed in the lower portion of the first trench by RIE, the depth of which is 5 탆 to 8 탆 from the surface of the semiconductor substrate. At this time, the oxide layer 19 for sidewall spacers is etched by the RIE process, leaving the spacers 19 only on the trench side walls.

Referring to FIG. 2f, after forming the second trench, the n ⁺ dopant is doped on the wall of the second trench to form a plate electrode of the lower capacitor at a concentration of 10 ¹⁹ to 10 ²⁰ # / cm 3 to form the n ⁺ diffusion electrode layer 21. Is formed in the n-type well 3. Subsequently, a second dielectric layer 23, for example, Ta ₂ O _5, is formed on the entire surface of the resultant, and a first conductive layer 25 for forming a first storage electrode, for example, a polysilicon layer is formed thereon.

Referring to FIG. 2G, the first storage electrode 25 is formed by applying the photoresist 27 to the entire surface of the resultant of FIG. 2F and performing an etch back process.

Referring to FIG. 2H, a region and a trench region to be the source diffusion layer 30 are exposed through a photolithography process to form the source diffusion layer 30. Subsequently, n ⁺ ion implantation is performed through the exposed region to form n ⁺ diffusion layer 30.

Referring to FIG. 2i, the photoresists 27 and 29 are removed and second conductive layers 31 for forming second storage electrodes are sequentially formed on the entire surface of the resultant. In this case, the second conductive layer for forming the second storage electrode may be formed of hemi-spherical grain (HSG), thereby maximizing capacitance. In this case, the thickness of the first conductive layer and the second conductive layer is adjusted to be smaller than the radius of the second trench to secure the capacitor area.

Referring to FIG. 2J, the nitride film which is a trench mask layer formed on the side of the second conductive layer and the field oxide film 11 formed in the regions other than the trench region and the activation region is removed by a photolithography process.

Referring to FIG. 2k, after removing the photoresist 37 used in the process of FIG. 2j, polishing the second conductive layer 31 until the nitride film 15 is exposed. A second dielectric layer 33, for example Ta ₂ O ₅ , is formed on the entire surface of the resultant.

Referring to FIG. 2L, polycrystalline silicon is deposited on the second dielectric layer 33 as a third conductive layer 35 for forming an upper plate electrode.

Referring to FIG. 2M, the third conductive layer 35 and the second dielectric film 33 are removed by performing a polishing or etch back process on the entire surface of the resultant product to form the nitride film 15 as an etch blocking layer. The nitride film 15 is exposed.

Referring to FIG. 2n, the remaining nitride film 15 is removed to form the upper plate electrode 35 in a self-aligned manner.

FIG. 2O is a view showing the trench region and the activation region, and shows that the process of forming the interlayer insulating film 39 and the bit line 41 is completed after the process of FIG. 2N is performed. Here, reference numeral 26 denotes a gate electrode and is formed at the same time during the first storage electrode 25 forming process, and reference numeral 32 is formed at the same time during the source diffusion layer 30 forming process as the drain region.

As described above, according to the present invention, in the method of manufacturing a DRAM cell having a double plate electrode structure, a triple well is used to arbitrarily adjust the bias of the lower capacitor electrode layer so that a minimum electric field is applied to the dielectric thin film for the capacitor. By using a double plate electrode, both the lower, upper, or side surfaces of the first storage electrode and the second storage electrode can be used as a capacitor, thereby increasing the capacitance and at the same time, topography, which is a problem of highly integrated DRAM cells. It can be greatly improved.

Claims (16)

A method of manufacturing an advanced DRAM cell, comprising: a first process of forming a first well of a second conductivity type on a first conductive semiconductor substrate and forming a second well of a first conductivity type in the first well; Forming a trench type isolation isolation film in the secondary well below the depth of the secondary well; A third process of sequentially forming a pad oxide film and a nitride film on the entire surface of the resultant, and then forming a first trench in a part of the active region through a photolithography process; A fourth step of forming a first conductive diffusion layer on an inner surface of the first trench at an impurity concentration higher than that of the secondary well; Forming a second trench under the first trench by forming an oxide film for the sidewall spacer on the entire surface of the resultant and performing anisotropic etching; A sixth step of forming a lower plate electrode by doping a second conductive type impurity on the inner surface of the second trench to a concentration higher than an impurity concentration of the first well; After forming a first dielectric film on the entire surface of the resultant and a first conductive layer on the first dielectric film. A seventh step of applying a photoresist to the entire surface of the resultant and etching back to form a first storage electrode; An eighth step of exposing a region to be a source diffusion layer and a trench region of the exciter transistor through a photolithography process and ion implantation to form a source diffusion layer of a second conductivity type; A ninth step of removing the photolist and then forming a second conductive layer on the entire surface of the resultant; A tenth step of removing the second conductive layer and the nitride film formed in the remaining regions except the trench region and the active region by a photolithography process; An eleventh step of removing the photoresist used in the tenth step, polishing the second conductive layer to expose the nitride layer, and then sequentially forming a second dielectric layer and a third conductive layer on the entire surface of the resultant; A twelfth step of exposing the nitride layer by polishing or etching back the third conductive layer and the second dielectric layer; And a thirteenth step of removing the remaining nitride film to form an upper plate electrode in a self-aligned manner. The method of claim 1, wherein the primary and secondary wells are formed by an epitaxial layer. The method of claim 1, wherein the first and second wells are formed by an ion implantation diffusion layer. The method of claim 1, wherein the depth of the first trench is formed deeper than the depth of the secondary well. The method of claim 4, wherein the first trench has a depth of about 1 μm to about 2 μm. The method of claim 1, wherein the impurity concentration of the diffusion layer formed by the fourth process is 10 ¹⁷ to 10 ¹⁹ # / cm 3. The method of manufacturing a highly integrated DRAM cell according to claim 1, wherein the oxide film for sidewall spacers has a thickness of 900 to 1,000 mW. 2. The method of claim 1 wherein the depth of the second trench is lower than the depth of the primary well. 9. The method of claim 8, wherein the depth of the second trench is between 5 [mu] m and 8 [mu] m from the surface of the semiconductor substrate. The method of claim 1, wherein the impurity concentration of the diffusion layer formed by the sixth process is 10 ¹⁸ to 10 ²⁰ # / cm 3. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are Ta ₂ O ₅ . The method of claim 1, wherein the first conductive layer and the third conductive layer are polycrystalline silicon. The method of claim 1, wherein the second conductive layer is HSG polycrystalline silicon. The method of claim 1, wherein the sum of the thicknesses of the first conductive layer and the second conductive layer is smaller than the radius of the second trench. The method of claim 1, wherein the lower plate electrode and the upper plate electrode are not connected to each other. The method of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.