KR950013134A - Data distribution transmission circuit - Google Patents

Data distribution transmission circuit Download PDF

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Publication number
KR950013134A
KR950013134A KR1019930021474A KR930021474A KR950013134A KR 950013134 A KR950013134 A KR 950013134A KR 1019930021474 A KR1019930021474 A KR 1019930021474A KR 930021474 A KR930021474 A KR 930021474A KR 950013134 A KR950013134 A KR 950013134A
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KR
South Korea
Prior art keywords
data
memory
counter
address
outputting
Prior art date
Application number
KR1019930021474A
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Korean (ko)
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KR0136393B1 (en
Inventor
박상용
Original Assignee
정장호
엘지정보통신 주식회사
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Application filed by 정장호, 엘지정보통신 주식회사 filed Critical 정장호
Priority to KR1019930021474A priority Critical patent/KR0136393B1/en
Publication of KR950013134A publication Critical patent/KR950013134A/en
Application granted granted Critical
Publication of KR0136393B1 publication Critical patent/KR0136393B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q1/00—Details of selecting apparatus or arrangements
    • H04Q1/18—Electrical details
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Communication Control (AREA)

Abstract

본 발명은 데이타 분배 전송회로에 관한 것으로, 특히 전자교환기 등과 같이 다수의 서브시스템(Sub-system)으로 이루어진 시스템에서 송신측 마이크로 프로세서가 데이타를 다수의 서브 시스템측으로 분배 전송하는 경우 송신측 마이크로 프로세서의 부하를 감소시킴과 동시에 데이타 전송메모리의 운용을 효율적으로 하도록 한 데이타 분배 전송회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data distribution transmission circuit. In particular, in a system composed of a plurality of sub-systems such as an electronic switch, when the transmitting microprocessor distributes and transmits data to a plurality of subsystems, The present invention relates to a data distribution transmission circuit which reduces load and makes efficient operation of a data transmission memory.

본 발명은 메모리의 메모리영역을 분할하여 사용하지 않으므로 메모리를 효율성있게 운용할 수 있고, 메모리에 데이타를 저장한 경우 필요한 메모리영역만을 어드레싱하고 메모리의 데이타를 출력하는 경우에도 해당 데이타만을 어드레싱하므로 마이크로 프로세서의 부하를 감소시킴과 동시에 데이타 전송속도를 향상시키게 된다.In the present invention, since the memory area of the memory is not divided and used, the memory can be efficiently operated. When the data is stored in the memory, only the required memory area is addressed and only the corresponding data is output even when the data of the memory is output. This reduces the load on the network and improves the data rate.

Description

데이타 분배 전송회로Data distribution transmission circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 데이타 분배 전송회로 구성도.2 is a block diagram of a data distribution transmission circuit according to the present invention.

Claims (1)

마이크로 프로세서로부터 공급된 데이타를 저장했다가 출력하는 메모리, 상기 메모리로부터 출력된 데이타를 상기 마이크로 프로세서의 제어에 따라 다수의 서브 시스템측으로 출력하는 버퍼 및, 상기 마이크로 프로세서로부터 공급되는 데이타 저장용 어드레스를 상기 메모리측으로 출력하는 선택부를 구비한 데이타 분배 전송회로에 있어서, 클럭을 분주하여 발생된 데이타 출력용 어드레스를 상기 선택부를 통해 상기 메모리측으로 출력하고 상기 마이크로 프로세서로부터 제어신호공급시 동일한 데이타 출력용 어드레스를 반복 출력하는 카운터, 상기 마이크로 프로세서로부터 공급된 데이타 출력용 최종어드레스를 저장하고 상기 카운터가 데이타 출력용 최종 어드레스를 출력할 때까지 상기 카운터를 동작시키는 비교부 및, 상기 비교부가 상기 카운터를 동작개시 시킬때 상기 카운터로부터 출력되는 데이타 출력용 초기어드레스를 래치하고 상기 카운터가 동일 어드레스를 반복 출력시키는 경우 상기 래치된 데이타 출력용 초기어드레스를 상기 카운터에 초기값으로 공급하는 래치를 구비하는 것을 특징으로 하는 데이타분배전송회로.A memory for storing and outputting data supplied from a microprocessor, a buffer for outputting data output from the memory to a plurality of subsystems under control of the microprocessor, and an address for storing data supplied from the microprocessor. A data distribution transmission circuit having a selector for outputting to a memory side, comprising: outputting a data output address generated by dividing a clock to the memory side through the selector and repeatedly outputting the same data output address when a control signal is supplied from the microprocessor; A comparator for storing a counter, a final address for outputting data supplied from the microprocessor, and operating the counter until the counter outputs a final address for outputting data; And a latch for latching a data output initial address output from the counter when the counter starts operation, and supplying the latched data output initial address to the counter as an initial value when the counter repeatedly outputs the same address. A data distribution transmission circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930021474A 1993-10-15 1993-10-15 Data transmission circuit KR0136393B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930021474A KR0136393B1 (en) 1993-10-15 1993-10-15 Data transmission circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930021474A KR0136393B1 (en) 1993-10-15 1993-10-15 Data transmission circuit

Publications (2)

Publication Number Publication Date
KR950013134A true KR950013134A (en) 1995-05-17
KR0136393B1 KR0136393B1 (en) 1998-06-01

Family

ID=19365944

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930021474A KR0136393B1 (en) 1993-10-15 1993-10-15 Data transmission circuit

Country Status (1)

Country Link
KR (1) KR0136393B1 (en)

Also Published As

Publication number Publication date
KR0136393B1 (en) 1998-06-01

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