KR930008618A - Multiple Cache Controllers in Tolerant Systems - Google Patents

Multiple Cache Controllers in Tolerant Systems Download PDF

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Publication number
KR930008618A
KR930008618A KR1019910017642A KR910017642A KR930008618A KR 930008618 A KR930008618 A KR 930008618A KR 1019910017642 A KR1019910017642 A KR 1019910017642A KR 910017642 A KR910017642 A KR 910017642A KR 930008618 A KR930008618 A KR 930008618A
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South Korea
Prior art keywords
data
output
system bus
control means
address
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KR1019910017642A
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Korean (ko)
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KR940005776B1 (en
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김병국
황종영
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정몽헌
현대전자산업 주식회사
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Publication of KR930008618A publication Critical patent/KR930008618A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

본 발명은 다중 UPU(Multi-User Processing Unit)를 구비하는 톨러런트 시스템(Tolerant System)의 다중캐쉬(Multi-Cache) 제어장치에 관한 것으로, 각 UPU마다 독자적으로 캐쉬를 제어할 수 있도록 하여 정상적인 메모리 억세스 동작이 가능하도록 하기 위한 것이다.The present invention relates to a multi-cache control apparatus of a tolerant system having a multi-user processing unit (UPU), and to allow a cache to be controlled independently for each UPU. This is to enable access operation.

따라서, 본 발명은 방향 제어수단(12), 데이타 래치수단(11), 및 어드레스 해독수단(13)을 구비하여 다중 캐쉬를 제어하는 다중 캐쉬 제어장치에 있어서, 그랜트라인 비지신호(BGNT*)와 시스템 버스 비지신호(BBSY*)를 입력으로 하고 상기 어드레스 해독수단(13)과 데이타 래치수단(11)에 연결된 출력제어수단(14)을 더 포함하여 구성되는 것을 특징으로 한다.Accordingly, the present invention is directed to a multiple cache control apparatus including a direction control means 12, a data latch means 11, and an address decoding means 13, for controlling multiple caches. And an output control means 14 connected to the address decoding means 13 and the data latching means 11 as a system bus busy signal BBSY *.

Description

톨러런트 시스템의 다중 캐쉬 제어장치Multiple Cache Controllers in Tolerant Systems

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 일반적인 톨러런트 시스템의 CPU 모듈의 구성도,1 is a configuration diagram of a CPU module of a general tolerant system,

제2도는 본 발명에 의한 다중 캐쉬 제어장치의 구성도.2 is a block diagram of a multiple cache control device according to the present invention.

Claims (2)

시스템 버스에 연결되어 데이타 이동시 데이타의 방향을 결정하는 방향 제어수단(12), 상기 방향 제어수단(12)과 시스템 버스와 슬레이브 포트 디바이스에 연결되어 방향 제어수단(12)의 출력에 따라 결정된 방향으로 데이타가 전송되도록 데이타를 일시 저장하는 데이타 래치수단(11), 및 상기 슬레이브 포트 디바이스에 연결되어 데이타 이동시 해당 어드레스를 디코딩하여 상기 해당 어드레스가 상기 슬라에이브 포트 디바이스에 해당하면 신호(SLVADD)를 출력하는 어드레스 해독수단(13)을 구비하여 다중 캐쉬를 제어하는 다중 캐쉬 제어장치에 있어서; 상대방 UPU 보드의 그랜트 라인(Grant Line)의 비지상태를 나타내는 그팬트라인 비지신호(BCNT*)와 시스템 버스 비지신호(BBSY*)를 입력으로 하고 상기 어드레스 해독수단(13)과 데이타 래치수단(11)에 연결되어 상기 그랜트 라인 및 시스템 버스의 상태에 따라 상기 어드레스 해독수단(13)으로 부터 출력되는 신호(SLVADD)를 상기 데이타 래치수단(11)의 출력 인에이블단자(/OE)에 인가하여 상기 데이타 래치수단(11)에 래치된 데이타가 출력되도록 하는 출력제어수단(14)을 더 포함하여 구성된는 것을 특징으로 하는 다중 캐쉬 제어장치.Direction control means 12 connected to the system bus to determine the direction of data when moving data, the direction control means 12 and connected to the system bus and the slave port device in the direction determined according to the output of the direction control means 12 A data latch means 11 for temporarily storing data so that data is transmitted, and connected to the slave port device to decode the address during data movement and output a signal SLVADD if the address corresponds to the slave port device. A multiple cache control device having an address decoding means (13) to control multiple caches; The address line deciphering means 13 and data latching means 11 are inputted with the pan line busy signal BCNT * and the system bus busy signal BBSY * indicating the busy state of the grant line of the other UPU board. Is connected to the output enable terminal / OE of the data latching means 11 by applying the signal SLVADD outputted from the address decoding means 13 according to the state of the grant line and the system bus. And multiple output control means (14) for outputting the latched data to the data latch means (11). 제1항에 있어서, 상기 출력 제어수단(14)은 상기 그랜트 라인 비지신호(BGNT*)를 데이타 입력으로 하고 상기 시스템 버스 비지신호(BBSY*)를 클럭 입력으로 하는 D플립플롭(17), 및 상기 어드레스 해독수단(13)에 입력단이 연결되고 상기 데이타 래치수단(11)에 출력단에 연결되고 상기 D플립플롭(17)의 출력단에 인에이블단자가 연결된 트랜시버(18)로 구성되는 것을 특징으로 하는 다중 캐쉬 제어장치.2. The D flip-flop (17) according to claim 1, wherein said output control means (14) is a D flip-flop (17) which uses the grant line busy signal (BGNT *) as a data input and the system bus busy signal (BBSY *) as a clock input. An input terminal is connected to the address decoding means 13, an output terminal is connected to the data latch means 11, and an enable terminal is connected to an output terminal of the D flip-flop 17. Multiple Cache Controls. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910017642A 1991-10-08 1991-10-08 Multi-cache controller in tolerant system KR940005776B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910017642A KR940005776B1 (en) 1991-10-08 1991-10-08 Multi-cache controller in tolerant system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910017642A KR940005776B1 (en) 1991-10-08 1991-10-08 Multi-cache controller in tolerant system

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KR930008618A true KR930008618A (en) 1993-05-21
KR940005776B1 KR940005776B1 (en) 1994-06-23

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