KR920001354A - Data Transmission Circuits and Methods - Google Patents

Data Transmission Circuits and Methods Download PDF

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Publication number
KR920001354A
KR920001354A KR1019900009187A KR900009187A KR920001354A KR 920001354 A KR920001354 A KR 920001354A KR 1019900009187 A KR1019900009187 A KR 1019900009187A KR 900009187 A KR900009187 A KR 900009187A KR 920001354 A KR920001354 A KR 920001354A
Authority
KR
South Korea
Prior art keywords
data
signal
processor
controlled processor
state
Prior art date
Application number
KR1019900009187A
Other languages
Korean (ko)
Other versions
KR920004415B1 (en
Inventor
음두찬
Original Assignee
강진구
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 강진구, 삼성전자 주식회사 filed Critical 강진구
Priority to KR1019900009187A priority Critical patent/KR920004415B1/en
Publication of KR920001354A publication Critical patent/KR920001354A/en
Application granted granted Critical
Publication of KR920004415B1 publication Critical patent/KR920004415B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

내용 없음.No content.

Description

데이타 전송회로 및 방법Data transmission circuit and method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1 도는 본 발명의 블럭도.1 is a block diagram of the present invention.

제 2 도는 볼 발명에 따른 흐름도.2 is a flow chart according to the invention of the ball.

제 3 도는 본 발명에 따른 동작 파형도.3 is an operational waveform diagram according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 데이타 저장보 20 : 저장 제어부10: data storage 20: storage control unit

30 : 응답신호 발생부 G1, G2 : 오아게이트30: response signal generator G1, G2: oragate

FF ; D : 플립플롭.FF; D: flip-flop.

Claims (2)

상호 데이타 전송 가능한 제어 및 피제어 프로세서로 이루어진 시스템에 있어서, 데이타 버스를 통해 입력되는 데이타를 저장하며 데이타 저장 상태를 나타내는 스테이터스 신호(STS)와 데이타 입력 완료신호(DIN)를 발생하는 데이타 저장부(10)와, 외부 제어 프로세서로부터 발생되는 스트로브 신호(STB)와 상기 데이타 저장부(10)의 상태를 나타내는 스테이터스 신호(STS)를 비교하여 상기 데이타 저장부(10)에서 데이타를 받아도 되는지의 여부를 지시하는 데이타 저장 제어 신호(DSC)를 발생하는 저장 제어부(20)와, 상기 데이타 저장부(10)로부터 발생되는 데이타 입력 완료신호(DIN)와 상기 저장 제어부(20)에 래치된 스트로브신호(STB)를 논리조합하여 전송 데이타 수신완료 상태를 나타내는 응답신호(ACK)를 발생하는 응답신호 발생부(30)로 구성됨을 특징으로 하는 피제어 프로세서의 데이타 전송회로.A system comprising a control and controlled processor capable of transmitting data to each other, comprising: a data storage unit for storing data input through a data bus and generating a status signal (STS) indicating a data storage state and a data input completion signal (DIN); 10) and the strobe signal STB generated from an external control processor and the status signal STS indicating the state of the data storage unit 10, are compared to determine whether or not the data storage unit 10 may receive data. A storage control unit 20 generating an instructed data storage control signal DSC, a data input completion signal DIN generated from the data storage unit 10, and a strobe signal STB latched by the storage control unit 20; ) And a response signal generator 30 for generating a response signal ACK indicating a transmission data reception completion state. Of the controlled processor, the data transfer circuit. 임의 제어 프로세서와 피제어 프로세서간의 데이타 전송 방법에 있어서, 상기 제어프로세서로부터 발생되는 스트로브신호와 상기 피제어 프로세서 내부 메모리의 저장상태를 표시하는 스테이터스신호의 상태에 따라 상기 제어프로세서로부터 상기 피제어 프로세서로 데이타전송이 시작되며, 데이타 수신 완료시 상기 피제어 프로세서로부터 제어프로세서로 응답신호를 송출함으로 특징으로 하는 방법.A data transfer method between an arbitrary controlled processor and a controlled processor, the method comprising: from the control processor to the controlled processor in accordance with a state of a strobe signal generated from the controlled processor and a status signal indicating a storage state of the internal memory of the controlled processor; A data transfer is initiated, and upon completion of data reception, sends a response signal from the controlled processor to the control processor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900009187A 1990-06-21 1990-06-21 A circuit and a method for transfering data KR920004415B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900009187A KR920004415B1 (en) 1990-06-21 1990-06-21 A circuit and a method for transfering data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900009187A KR920004415B1 (en) 1990-06-21 1990-06-21 A circuit and a method for transfering data

Publications (2)

Publication Number Publication Date
KR920001354A true KR920001354A (en) 1992-01-30
KR920004415B1 KR920004415B1 (en) 1992-06-04

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ID=19300366

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900009187A KR920004415B1 (en) 1990-06-21 1990-06-21 A circuit and a method for transfering data

Country Status (1)

Country Link
KR (1) KR920004415B1 (en)

Also Published As

Publication number Publication date
KR920004415B1 (en) 1992-06-04

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