KR950012764A

KR950012764A - Method of manufacturing thin film transistor

Info

Publication number: KR950012764A
Application number: KR1019930022653A
Authority: KR
Inventors: 채기성
Original assignee: 이헌조; 주식회사 금성사
Priority date: 1993-10-28
Filing date: 1993-10-28
Publication date: 1995-05-16

Abstract

본 발명은 박막트랜지스터에 관한 것으로, 종래의 박막트랜지스터는, 상기 소오스/드레인전극의 모서리에 발생하는 자계의 집중현상으로 인해 박막트랜지스터의 안정성이 떨어지는 문제가 있었다.The present invention relates to a thin film transistor, the conventional thin film transistor has a problem that the stability of the thin film transistor is poor due to the concentration of the magnetic field generated at the corner of the source / drain electrode.

본 발명은 이러한 문제점을 해결하기 위하여 소오스/드레인전극과 반도체층 사이에 절연막을 형성하여 소오스/드레인전극의 모서리가 반도체층과 직접 접촉하지 않게 함으로써 자계의 집중현상을 제거하거나 상기 형성하여 자계의 집중현상을 제거하며 박막트랜지 소오스/드레인전극의 모서리를 테이퍼 에칭하여 테이퍼로스터의 동작안정성을 높일 수 있도록 한 박막트랜지스터 제조방법을 창안한 것이다.In order to solve the problem, the present invention forms an insulating film between the source / drain electrodes and the semiconductor layer so that the edges of the source / drain electrodes do not come into direct contact with the semiconductor layer, thereby eliminating or concentrating the magnetic field. The present invention devised a method for manufacturing a thin film transistor which eliminates the phenomenon and increases the operational stability of the tapered roaster by tapering etching edges of the thin film transistor source / drain electrodes.

Description

Method of manufacturing thin film transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도의 (가) 내지 (라)는 본 발명 박막트랜지스터의 제조공정도.Figure 3 (a) to (d) is a manufacturing process diagram of the thin film transistor of the present invention.

제4도는 제3도의 있어서, 드레인측부분단면도.4 is a drain side partial sectional view of FIG.

제5도는 제4에 대한 다른 실시예도.5 is another embodiment of the fourth embodiment.

Claims

Forming a gate electrode on the substrate, forming a gate insulating film, forming a source / drain electrode pattern, and forming a second gate insulating film on the gate electrode so as to span the source / drain positive electrode. A process of depositing a semiconductor layer after depositing a semiconductor layer, forming a contact hole so as to expose the source / drain electrodes after depositing a protective insulating film, and forming a metal electrode on the contact hole. The thin film transistor manufacturing method, characterized in that made.

Forming a gate electrode on the substrate, and forming a gate insulating film; Tapering edges in contact with the semiconductor layer by depositing source / drain electrodes; depositing patterned islands after depositing the semiconductor layer; and contacting the source / drain electrodes to be exposed after depositing a protective insulating film. And forming a metal electrode over the contact hole.

※ Note: The disclosure is based on the initial application.