KR950010593Y1 - A nonvolatile semiconductor memory device having a misswrite preventing function - Google Patents

Abstract

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Description

Nonvolatile Semiconductor Memory with False Recording Protection

1 is a circuit diagram according to a first embodiment of the present invention.

2 is a circuit diagram according to an actual pattern.

3 is a plan view showing the pattern of FIG. 2 and a cross-sectional view taken along lines B-B and A-A.

4 is a circuit diagram according to the actual pattern of the second embodiment of the present invention.

5 is a plan view of the circuit diagram shown in FIG. 4, and a sectional view taken along lines B-B and C-C.

6 is a circuit diagram according to the actual pattern of the third embodiment of the present invention.

7 is a plan view showing a part of a conventional example, and sectional views taken along lines B-B and A-A.

8 and 9 are equivalent circuit diagrams and equivalent circuit diagrams of a capacitive system.

10 is a circuit diagram showing a part of a conventional memory cell array.

11 is a circuit diagram of a conventional memory.

12 is a plan view of a conventional memory cell and cross-sectional views of lines B-B and C-C.

* Explanation of symbols for main parts of the drawings

11: floating gate 13: control gate

15 source 16: drain

30: floating gate transistor 31-1 to 31-k: block

42-1 to 42-k: block select transistor

44-1 to 44-k: Decoder decoder (erase signal applying means)

45-1 to 45-k: Block select decoder DL1 to DLn: Data line

[Industrial use]

The present invention relates to a nonvolatile semiconductor memory device capable of electrically erasing data. In particular, the present invention relates to a nonvolatile semiconductor memory device having a write error prevention function that prevents malfunction of an unselected cell by shortening the time that a voltage stress is applied to the unselected cell. A volatile semiconductor memory device.

[Traditional Technology and Problems]

The EEPROM (Electrically Erasable and Programmable ROM), which can erase the stored data electrically and rewrite, is easy to use because it can be erased by electric signal while assembled on the board, compared to the UV erasure type EPROM. The demand for IC cards (memory cards) is increasing rapidly. In particular, memory cells as shown in Figs. 7A to C are used to realize the large capacity of the EEPROM.

FIG. 7A is a pattern plan view, FIG. 7B is a cross sectional view taken along the line B-B shown in FIG. A, and FIG.

In the drawing, reference numeral 11 denotes a floating gate composed of a polysilicon layer of a first layer, 12 an erase gate composed of a polysilicon layer of a second layer, and 13 a control gate composed of a polycrystalline silicon layer of a third layer. The control gate 13 is also used as a word line of a memory cell.

Further, reference numeral 14 denotes a P-type substrate, 15 and 16 are sources and drains formed of an N ⁺ type diffusion layer formed on the substrate 14, 17 is a contact hole, and 18 is the medium via the contact hole 17. It is a data line made of an aluminum layer connected to the drain 16. Reference numeral 19 is a gate insulating film of 300 kV as the gate insulating film of the floating gate transistor portion, reference numeral 20 is a gate insulating film provided between the floating gate 11 and the erasing gate 12, and has a thickness of 350 kPa. The gate insulating film provided between the gate 11 and the control gate 13 is composed of a three-layer structure film of ONO structure (Oxide-Nitride-Oxide). Reference numeral 22 denotes a gate insulating film provided between the erase gate 12 and the control gate 13, which also has an ONO structure, and reference numeral 23 selects the third polycrystalline silicon layer 13 as a gate electrode. 24 is a field insulating film and 25 is an interlayer insulating film.

On the other hand, the equivalent circuit of the memory cells shown in Figs. 7A to 7C is shown in Fig. 8, and the equivalent circuit of the capacitance system is shown in Fig. 9.

In FIG. 8, VD is a drain potential, VS is a source potential, V _FG is a floating gate potential, V _EG is an erase gate potential, and V _CG is a control gate potential. In FIG. 9, C _FC is the capacitance between the floating gate 11 and the control gate 13, C _FE is the capacitance between the floating gate 11 and the erase gate 12, C _FD is the floating gate 11 The capacitance between the drain and the drain 16, C _FS, is the other capacitance seen from the floating gate 11.

In this capacity system, the initial value Q (I) of the charge amount accumulated in the total capacity is given by the following equation.

Q (I) = (V _FG -V _CG ), C _FC + (V _FG -V _EG ), / C _FE

+ (V _FG -V _D ) · C _FD + (V _FTG -V _S ) · C _FS . (One)

If the total of the total doses is CT, CT is given by the following equation.

C _T = C _FC + C _FE + C _FD + C _FS . (2)

Therefore, the voltage VFG applied to the floating gate is given by the following equation.

V _FC = {(V _CG ㆍ C _FC + V _EG ㆍ C _FE + V _D ㆍ C _FD )

+ V _{S .C FS} ) / C _T } + {Q (I / C _T }… (3)

Here, if Q (I) / C _T = V _FG (I) and V _S = O _V are substituted, Equation (3) is as follows.

V _FG = {(V _CG C _FC + V _EG C _FE + V _D C _FD ) / C _T } + V _FG (I). (4)

The memory cells as described above are replaced by a matrix in the actual memory cells.

For simplicity, a four-bit memory cell array having four memory cells M1 to M4 as shown in FIG. 10 is considered. The drain 16 of these four memory cells M1 to M4 is considered. Is connected to any one of the two data lines DL1 and DL2, the control gate 13 is connected to any one of the two word lines WL1 and WL2, and the erase gate 12 is the erase line EL. Are commonly connected to, and a reference voltage (for example, O _V ) is applied to the source 15.

In the memory cell array configured as described above, data erasing is collectively performed for all the memory cells M1 to M4. That is, the source potential V _S , the drain potential V _D , and the control gate potential V _CG of each memory cell are set to O _V (that is, data lines DL1 and DL2) and word lines WL1 and WL2, respectively. _{It is set to V} , and the erase gate potential (V _EG ) is set to a high potential (for example, + 2O _V ). At this time, the electrons in the floating gate 11 are discharged toward the erasing gate 12 by the field emission due to the tunnel effect of the Howler nodeheim, and the floating gate 11 is charged to the electrostatic potential.

If the potential V _FG (I) in the floating gate 11 is set to + 3V, for example (the threshold value V _TH of the floating gate transistor is 1v), a safety layer is provided below the floating gate 11. The threshold voltage of the memory cells M1 to M4 decreases, and this state is assumed to be stored in the data "1".

Next, a case of selecting one memory cell, for example M1, from among a memory cell array and writing data therein is considered. When data is written to the selected cell M1, the control gate potential (V _CG ; potential of the word line WL1) of the memory cell is set to a high potential, for example, +12.5 V, and the drain potential V _D ; (Potential of DL1) is set to a high potential, for example, +10 _V , and the potential of the source voltage V _S and the data line DL2 and the potential of the word line WL2 are set to O _V , respectively. In addition, the erase gate potential V _FG is set to + 5V, for example. As a result, in the selection cell M1, the potential of the floating gate 11 is raised to facilitate recording. Then, a hot electron effect is caused in the vicinity of the drain 16 of the selection cell M1, and electrons generated by the impact ionization are injected into the floating gate 11 so that the floating gate 11 is negative. It is assumed that the potential V _FG (I) in the floating gate 11 is, for example, -3V.

In such a state, the threshold voltage of the memory cell M1 becomes high, and this state is assumed to store data "0". In this case, the hot electron effect is not caused in the non-selected cells M2 to M4.

Next, in the data writing, the voltage stress applied to the unselected cells M2 to M4 is considered. At the time of recording, V _EG. V _EF and V _D. C _FD of the above formula (4) are sufficiently small compared with V _CG .C _FC .

V _FG = (C _FC / C _T ) V _CG + V _FG (I)... (5)

Here, the capacity ratio _(FC C / C _T), for example 0.6, and in the "1" cell, _{V FG (I) = + 3V} , the "0" cell V _FG (I) = - and to 3V. Further, the case where the data of the predetermined non-selected cell M2 is "1" on the same word line WL1 as the selected cell M1 is considered.

Since the control gate potential V _CG of M2 is 12.5 V, the floating gate potential V _FG becomes 10.5 V by the above equation (5). Therefore, since the erase gate potential V _EG is 5V, the potential of the erase gate 12 seen from the floating gate 11 is -5.5V.

In this way, by applying 5 V to the erase gate 12, the electric field of the floating gate 11 of the floating gate 11 of the predetermined non-selected cell M2 on the same word line WL1 as the selected cell M1 is reduced. Is relaxed. Therefore, it is possible to prevent the malfunction caused by the miswriting and the reliability is improved. On the other hand, the voltage stress applied between the drain 16 and the floating gate 11 varies greatly depending on whether the data of the memory cell is applied to "1" or "0". Here, Table 1 shows the voltage stress of the floating gate 11 of the drain 16 applied to the four memory cells M1 to M4 in FIG.

TABLE 1

In Fig. 10, the maximum voltage stress of the floating gates of the unselected cells M2 to M4 is that the control gate is connected to a word line WL2 that is different from the word line WM1 of the selected cell M1. The data is " 0 " in the non-selected memory cell M3. That is, as can be seen from Table 1, in the unselected cell M3, a voltage of +13.0 V is applied between the floating gate 11 and the drain 16, and electrons in the floating gate 11 are applied to the drain 16. If it is easily released, an erasure will occur.

Next, the strict conditions are the case where the data of the memory cell M2 is "1". In this state, electrons are injected into the floating gate 11, and there is a possibility that miswriting occurs.

FIG. 11 is a circuit diagram showing a conventional configuration of a memory using the memory cell, wherein the drain 16 of each cell 30 in the memory cell array 31 in the drawing is any one of n data lines DL1 to DLn. The control gate 13 is connected to any one of the m word lines WL1 to WLm. The erase gates 12 of the memory cells 30, 30 --- are commonly connected to the erase line EL, and a reference voltage, for example, O _V, is applied to the source 15.

Since the erase gates 12 of all the memory cells 30 in the memory cell array 31 are common, in the case of data writing, V _EG is simultaneously applied to the erase gates of all the memory cells 30. In Fig. 11, reference numeral 32 denotes a row decoder, 33 denotes a column decoder, 34-1 to 34-n denotes a column select transistor, 35 denotes a bus line, 36 denotes data input, 37 denotes an amplifying circuit, and 38 denotes 39 is an erase booster circuit, and 41 is an address buffer.

Here, let t be the data write time per cell (1 bit), and consider the case of writing for all the sequential bits. In the non-selected memory cell (M3 in Table 1), the stress time at which the control gate 13 becomes OV and the drain 16 is 1OV, that is, the stress time in the erased state described in Table 1 above per bit (M-1) x t at maximum (per one cell). In addition, 12.5V of the control gate 13 and the drain 16 of the control gate 13 of the memory cell M2 of Table 1 are OV, that is, the stress time in the false recording state of Table 1 is at most (n-1) × per bit. it becomes t. Here, m is a runner as described above, and n is a runner.

For example, in the case of a memory of 1M bits (128K words x 8 bits), n = 128 and m = 1024. If the recording time of one bit is set to 1 ms, the stress time in a state where there is a risk of erasing,

1 ms × (1024-1) = 1.023 S... … (a)

It becomes In addition, the stress time that there is a possibility of misrecording,

1㎳ × 127 = 127㎳

It becomes In this case, considering that the thickness of the insulating film of the floating gate 11 is 300 것을, and considering that the probability that the erase and miswriting can occur is proportional to the stress time, the level of reliability is satisfactory.

12A to C show an EEPROM having no erase gate as the second conventional example. Here, the same reference numerals are attached to the same parts as those in FIGS. 7a to c, and detailed description thereof will be omitted.

The difference from the EEPROM cells of FIGS. 7A to C is that there is no erase gate, there is no selection transistor having the control gate 13 as a gate, and the floating gate 11 is in direct contact with the source 15 and the drain 16. In addition, the floating gate insulating film 19 is thinned to about 100 mW.

Next, the operation principle of FIGS. 12A to C will be described.

At the time of erasing, the erasing voltage 1OV is applied to the source 15, the drain 16 is floating and the control gate 13 is OV. Accordingly, as a high voltage is applied between the floating gate 11 and the source 15 through the thin floating gate insulating film 19, electrons of the floating gate 11 are attracted to the source 15 due to the tunnel effect of the Howler nodeheim. Is released toward < RTI ID = 0.0 >

At the time of writing, the drain 16 is about 6V, the source is OV, and the control gate 13 is 12V. Thus, hot electrons generated in the vicinity of the drain 16 are injected into the floating gate 11 to record. Is performed.

In addition, when reading the drain 16, the source 15 is set to OV, and the control gate 13 is set at 5V, data "1" or "1" is read out depending on the presence or absence of electrons in the floating gate 11. do.

When the array is formed using this memory cell, the erase line EL may be connected to the common source V _S of all the melomicells while being replaced. Accordingly, batch erasing is performed for all memory cells.

The first prior art as described above technique, by chip erase of the memory cell is the stress state of all memory cells Cree record and erase (hereinafter referred to it as a W / E) repeating example 10 ⁴ times carried out also stress the accumulation of Without it, no problems are caused. However, in batch erasing, it is difficult to use because the memory cells that are not to be erased are erased.

In addition, there is a problem that restrictions occur in terms of application. In order to solve this problem, the memory cell area may be divided into a plurality of small areas (hereinafter, referred to as blocks) and erased by this block unit (hereinafter, referred to as block erasure). Specifically, for example, two word lines may be used. The erase gates of the memory cells connected to their word lines are commonly connected to each other. During erasing, an erase voltage V _EG = 2OV may be selectively applied to one of the common erase lines by an erase decoder (not shown).

As a result, block erasing for erasing only memory cells belonging to the selected block can be performed. In the case of dividing the cells into blocks in this manner, the time when stress is applied to the unselected cells is considered. First, consider the stress time of the false record concern (see Table 1). This stress time is the same as in the case of batch erasing which performs block division.

Next, consider the stress time of concern (see Table 1). The stress is a maximum of the selected block (here, the word lines 2 cups) all blocks other than the case of (word line 1022 minutes), repeated 10 ⁴ times a W / E. So the maximum of that time is

1㎳ × 1022 × 104 = 10200 seconds

As the maximum stress is applied, there is a high risk of causing an erasure.

Also, as the second conventional example, the EEPROM shown in Figs. 12A to C is suitable for miniaturization because the memory cell is composed of only two-layer polysilicon, but when the block is erased by block as described above, The stress applied is large. In particular, since the insulating film 19 is as thin as 100 kHz, block erasing is difficult.

[Purpose of designation]

The present invention has been devised in view of the above, and the memory cell array is composed of a plurality of blocks, and the stress at the time of writing is not applied to the unselected block so that the memory cells at the time of writing are not caused to malfunction. The purpose is to provide a highly reliable nonvolatile semiconductor memory.

[Purpose of designation]

A nonvolatile semiconductor memory device having a write protection function according to the present invention for achieving the above object includes a floating gate 11, a control gate 13 and a drain 16 capacitively coupled to the floating gate 11. ) And a source 15 to electrically perform data exchange by recording by injection of electrons into the floating gate 11 and erasing by emission of electrons from the floating gate 11. A nonvolatile semiconductor memory device in which a floating gate transistor 30 capable of being used as a memory cell and a plurality of memory cells is used to form a memory cell array, wherein the memory cell array is a plurality of arbitrary numbers of the memory cells. Is divided into blocks 31-1 to 31-k, and the plurality of memory cells in each of the blocks 31-1 to 31-k are connected in common to each other in the column direction. Each drain of each of the memory cells arranged in the column direction while forming the through source 46 is connected in common to form a common drain line 43. The data lines DL1 to DLn for transmitting a write signal and the Block selection transistors 42-1 to 42-k for connecting the common drain line 43 and the data lines DL1 to DLn, and from the data line for injecting electrons into the floating gate 11; A block selection decoder 45-1 to 45-k for selecting the block selection transistor to apply a write signal only to a common drain line connected to a selected memory cell in the block, and a source commonly connected among the blocks; A source selection transistor 47 for connecting the source Vss ^* is provided.

[Action]

According to the present invention configured as described above, a memory cell array composed of a plurality of memory cells (floating gate transistors) is divided into blocks composed of a plurality of memories, and in each block, memory cells in the blocks are collectively erased. . In addition, since the write signal (stress) is not applied to the drain in the other blocks when writing to the predetermined memory cell in the predetermined block, the reliability as the memory cell itself is improved.

EXAMPLE

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

In the embodiment of the present invention, the memory cell array is divided into a plurality of blocks, which are electrically erasable in units of blocks, and the voltage stress is not applied to the unselected block during writing. High reliability is achieved for the W / E replacement cycle.

1 shows a first embodiment of the present invention, the same reference numerals are attached to the same parts as in FIG. 11, and detailed description thereof will be omitted.

The memory cell arrays 31-1 to 31-k are connected to the row decoders 32-1 to 32-k, respectively, by integrating a plurality of word lines (two in this case) into one, and in each block (each memory cell). The erase gates of the memory cells in the arrays 31-1 to 31-k are connected to the erase lines EL1 to ELK while being connected in common in the block.

The erase decoders 44-1 to 44-k are for selecting one of these erase lines EL1 to ELk, and drains of the memory cells 30 in each block are respectively provided to the common drain 43. Each common drain 43 is connected to the data lines DL1 to DLn through the array select transistors 42-1 to 42-n. Here, the gates of the block selection transistors 42-1 to 42-n are connected in common to each block to form block selection lines BSL1 to BSLk. These selection lines BSL1 to BSLk are connected to the block selection coders 45-1 to 45-k, respectively, and the other configurations are the same as those in FIG.

Next, the operation of the apparatus will be described.

For example, a case of erasing a block of the cell array 31-1 will be described.

In this case, the first decoder emitter (44-1) is selected for being erased, the erase line (EL1) erase voltage; to be applied (V _EG approximately 20V), that is erase decoder (44-2~44-k) for other Non-selection causes the erase lines EL2 to ELk to become OV.

Further, in each of the arrays 31-1 to 31-k, all word lines become O _V to become block selection lines BSL1 to BSLk, and the common drain 43 is about OV. Accordingly, all the memory cells of the memory cell array 31-1 are erased at the same time.

Next, the recording will be explained. For example, when writing to the Merolicell M1 of the array 31-1, the data input Din is set to "0". Here, the write voltage is output from the data input circuit 36 so that the common bus line 35 is 12V, and the column select line CL1 is selected by the column decoder 33 to be 12V, and the block select decoder ( 45-1) is selected to set the block select line BSL1 to 12V. The data line DL1 is set to 1OV by the selection of the column selection line CL1, and the common drain 43 connected to the transistor 42-1 is also set to 1OV by the selection of the block selection line BSL1. do.

In addition, as the word line WL1 is selected by the row decoder 31-1 and becomes 12V, writing is performed to the selected memory cell M1.

On the other hand, since the unselected block selection lines BSL2 to BSLk are OV, all the block selection transistors 42-1 to 42-n of the cell arrays 31-2 to 31-k of the unselected blocks are turned off. It becomes. Therefore, in the cell arrays 31-1 to 31-k of the non-selection block, all common drains 43 are about OV (floating state). No voltage stress is applied to the drain of each cell 30.

Next, reading will be described. Here, it is assumed that data is read from the memory cell M1. At this time, as the block select decoder 45-1 is selected, only the block select line BSL1 becomes 5V, and the other block select lines BSL2 to BSLk become unselected and OV.

The word line WL1 of the selected block 31-1 is selected by the row decoder 32-1 to be 5V, and the data line DL1 is selected by the column selection line CL1 by the column decoder 33. Is selected, information is read from the selected memory cell M1. At this time, all of the block selection transistors 42-1 to 42-k in the unselected blocks 31-2 to 31-k are turned off. As a result, in the other arrays 31-2 to 31-k, the parasitic capacitance in contact with the data line DL1 is greatly reduced because the common drain 43 is separated from the data line DL1.

As a result, the charge / discharge time of the data line DL1 is shortened, so that reading from the memory cell M1 is performed at high speed. However, if the read speed may be low, all the block select lines BSL1 to BSLk may be 5V.

For example, when the 1M bit memory is configured as shown in FIG. 1, the stress time applied to the cell M3 is compared with that of the conventional FIG. The stress is applied to the cell M3 only when the cell M1 in the same block 31-1 is to be the date recording target, and any cell in the other blocks 31-2 to 32-k is to be recorded. In this case, no stress is applied to the cell M3. Therefore, the stress time applied to M3 is one recording time in the case of FIG. 1 (when two word lines are connected to one row decoder). If the recording time is 1 ms as before, the stress time is naturally 1 ms. It can be seen that this is significantly smaller than 1.023S in the conventional formula (a). Therefore, the cell M3 is not actually erased.

FIG. 2 is a circuit diagram showing a part of an example in which the circuit of FIG. 1 is actually laid out, and FIGS. 3A to 3C are a plan view and a cross-sectional view of the layout corresponding to the circuit portion of FIG. That is, FIG. 3A is a plan view, FIG. 3B is a sectional view taken along the line B-B, and FIG. 3C is a sectional view taken along the line C-C. In Figs. 3A to C, the same reference numerals are attached to the same parts as Figs.

In particular, as can be seen from FIG. 2, four word lines are included in one block. There are four memory cells connected to one word line (eg, DL1) through the block select transistor 42-1. In particular, the layout characteristic shown in FIG. 3A is that the common drain 16 of these four memory cells is connected to only the diffusion layer 16A and is in contact with the A1 line. The common drain 16 is connected to the diffusion layer 16A through the block select transistor 42-1, and the diffusion layer 16A is connected to the data line 18 (AL) DL via the contact 17. It is connected. As a result, one contact 17 is provided for eight transistors in both the upper and lower blocks. In other words, the number of contacts becomes 1/4, which effectively works under the reduction of the pattern. In addition, the source 15 of each cell 30 is commonly connected in the diffusion layer 15A, and is connected to the Vss line 26 (Al) via a contact 17A. 4 illustrates another embodiment in which block erasing is possible, which corresponds to FIGS. 12a to c without an erase gate. 4 differs from FIG. 2 in that the source selection transistor 47 is provided between the common source line Vss ^* and the common source 46 of the memory cells in the block. The data of this transistor 47 are connected to each block in common, and are connected to source select lines SSL1 to SSLk (only SSL2 and SSL3 are shown).

Next, operation of FIG. 4 will be described.

In FIG. 4, it is assumed that blocks of word lines WL5 to WL8 are selected.

At the time of erasing, the block select line BL2 and the word lines WL5 to WL8 are set to OV, the source select line SSL2 is 12V, and the common source line Vss ^* is 12V. The source select lines SSL1 and SSL3 to SSLk of the unselected block are both OV. In this state, about 1OV is applied only to the common source line 46 of the selected block, and the memory cell 30 is erased in the selected block. On the other hand, in the unselected block, erase is not performed because it is not applied to the source of the memory cell.

Next, the case of recording in the cell M2 will be described.

Here, the data line DL1 and the word line WL5 are selected to be DL1 = 6V and WL = 12V, and the block select line BSL2 and the source select line SSL2 are selected to be 12V, respectively. Vss ^* ) becomes OV. Accordingly, writing is performed to the memory cells 30 (M1).

At this time, since the block selection lines BSL1 and BSL3 to BSLk of the other blocks are all OV, even if the data line DL1 is 6V, no stress is applied to the drain of the memory cell 30 of the unselected block. Do not. Here, the source selection lines SSL1 and SSL3 to SSLk of the non-selection block are preferably set to Ov. However, even when turned on, no particular problem occurs.

5a to c show the actual layout of FIG. 4, that is, FIG. 5a is a plan view, FIG. 5b is a sectional view taken along line B-B, and FIG. 5c is a sectional view taken on line C-C.

In these figures, the basic arrangement is the same as those of FIGS. 3A through C, but in particular, the difference is that the common source line 27 (Vss ^* ) is performed by the second AL, and the data lines DL1 through DLn are performed by the first AL, The common source line Vss ^* is replaced with the data lines DL1 to DLn. In this way, the cell pitch in the lateral direction can be determined by the pitch of the first Al wiring of the data lines DL1 to DLn, and the cell size can be reduced.

Contrary to the above, A 1 of the first layer may be used as the common source line Vss ^* , and A 1 of the second layer may be used as the data line. In addition, the common source line Vss ^* can be made parallel to the data line as shown in FIGS. 3A to 3C. In this way, even if the cell size is slightly sacrificed, wiring can be performed by A1 of a single layer, thereby facilitating the process. 6 shows another embodiment, which differs from FIG. 4 in that instead of providing a source selection line and a source selection transistor, a source line dedicated to the memory cell common source 46 for each block (Vss ^* 1 to Vss ^* k). ; Only Vss ^* 2 and Vss ^* 3 are shown).

Next, operation of FIG. 6 will be described. In erasing, a high voltage is applied to only the common source line of the selected block, and the block is erased. For example, if the blocks of the word lines WL5 to WL8 are selected, only the common source line Vss ^* 2 is selected by the erasing decoder (not shown), and 1OV is applied thereto to erase the memory cells. The common source lines (Vss1, Vss ^* 3 to Vss ^* k) of the other blocks are OV and erase is not performed. At the time of recording and reading, the common source lines (Vss ^* 1 to Vss ^* k) are both OV. Except for this point, each signal is the same as that of FIGS. 3A to 3C. In this sixth example, a separate common source line (Vss ^* 1~Vss ^* k) is wired in a perpendicular direction to the first layer Aℓ, and the 5a-c help Like the data lines by the second layer Aℓ.

The common source line according Although not shown, in Figure 6 (Vss ^* 1~Vss ^* k), and to be used in common in the up and down direction, and wired in parallel to the data line (DL1~DLk), thereby Aℓ 1 It can be wired to a layer, and it becomes easy in a process. At this time, since block erasing is not possible, all cells are collectively erased. If block erasing is performed, the common source line Vss ^* is set to 1OV, only word lines for the selected block are set to OV, and only word lines WL5 to WL8 are set to OV, and word lines for other non-selected blocks are set to OV. All of WL1-WL4 and WL9-Lm are 12V. As a result, the voltage between the floating gate 11 and the source 15 of the memory cell of the unselected word line becomes significantly smaller than the voltage of the selected cell. As a result, the memory cells of the unselected word lines are not erased, and block erasing of only the memory cells of the selected word lines is performed.

On the other hand, the reference numerals written in each component of the claims of the present application to facilitate the understanding of the present invention, not intended to limit the technical scope of the present invention to the embodiments shown in the drawings.

[Effect of design]

As described above, according to the present invention, when a memory cell is divided into blocks and a write operation is performed in a predetermined memory cell of a predetermined block, a write voltage (stress) is not applied to the memory cells of the other blocks. When writing to a certain cell, malfunctions in other cells can be prevented, thereby improving the reliability of the entire memory.

Claims (2)

The floating gate 11, the control gate 13, the drain 16, and the source 15, which are capacitively coupled to the floating gate 11, are provided with electrons into the floating gate 11. A plurality of memory cells are used as a memory cell using a floating gate transistor 30 capable of electrically performing data exchange by writing and erasing by emission of electrons from the floating gate 11. In a nonvolatile semiconductor memory device comprising a memory cell array, the memory cell array is divided into a plurality of blocks 31-1 to 31-k for each arbitrary number of the memory cells, and each of these blocks In the plurality of memory cells of 1 to 31-k, each source of each memory cell arranged in the column direction is commonly connected to each other, and the drains of each memory cell in the column direction are connected in common while forming a common source 46. Been each Each common drain line 43 is constituted, and a block selection transistor for connecting the data lines DL1 to DLn for transmitting a recording signal and the common drain line 43 and the data lines DL1 to DLn is provided. 42-1 to 42-k), selecting the block to apply a write signal from a data line for injecting electrons into the floating gate 11 only to a common drain line connected to a selected memory cell of the block; Block selection decoders 45-1 to 45-k for selecting a transistor, and a source selection transistor 47 for connecting a common source line and a common source line Vss ^{* of} each block. Non-volatile semiconductor memory device with a false write protection function. 2. The memory cell array of claim 1, wherein the memory cell array is configured such that the memory cells are arranged in rows, and the blocks 31-1 to 31-k are configured by any number of row units of the memory cells. A nonvolatile semiconductor memory device having a write protection function.