KR950010054A - Methods and systems for protecting integrated circuits from various electrical transients - Google Patents

Methods and systems for protecting integrated circuits from various electrical transients Download PDF

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KR950010054A
KR950010054A KR1019940022903A KR19940022903A KR950010054A KR 950010054 A KR950010054 A KR 950010054A KR 1019940022903 A KR1019940022903 A KR 1019940022903A KR 19940022903 A KR19940022903 A KR 19940022903A KR 950010054 A KR950010054 A KR 950010054A
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circuit board
integrated circuit
high voltage
voltage pulse
board region
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KR100331661B1 (en
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듀버리 차바카
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윌리엄 이. 힐러
텍사스 인스트루먼츠 인코포레이티드
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13034—Silicon Controlled Rectifier [SCR]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

고전압 펄스 보호 디바이스(10)은 집적회로(28 및 30)을 보호한다. 집적회로(28 및 30)은 집적회로 기판 영역(64)와 결합된다. 고전압 펄스 보호 디바이스(10)은 집적회로 기판 영역(64)로부터 분리되는 보호 회로 기판 영역(74)를 포함한다. 주 보호 회로(40 및 42)는 보호 회로 기판 영역(74)와 결합되어, 고전압 펄스를 수신하고 이를 최소한 1개 이상의 접속부를 통해 소산시키기 위해 집적회로(28 및 30)과의 최소한 1개 이상의 접속부(22)를 포함한다. 이는 고전압 펄스로부터 집적회로(28 및 30)을 보호한다.The high voltage pulse protection device 10 protects the integrated circuits 28 and 30. Integrated circuits 28 and 30 are coupled with integrated circuit board region 64. The high voltage pulse protection device 10 includes a protection circuit board area 74 separated from the integrated circuit board area 64. Main protection circuits 40 and 42 are coupled with protection circuit board area 74 to provide at least one connection with integrated circuits 28 and 30 to receive high voltage pulses and dissipate them through at least one connection. (22). This protects the integrated circuits 28 and 30 from high voltage pulses.

Description

여러가지 전기적 과도 현상으로부터 집적회로를 보호하기 위한 방법 및 시스템Methods and systems for protecting integrated circuits from various electrical transients

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 실시예의 개념도.1 is a conceptual diagram of an embodiment of the present invention.

제2도는 본 발명의 한 실시예의 전기적 개략도.2 is an electrical schematic diagram of one embodiment of the present invention.

제3도는 제2도의 실시예의 가능한 기판 구성을 개념적으로 도시한 도면3 conceptually illustrates a possible substrate configuration of the embodiment of FIG.

Claims (20)

고전압 펄스로부터 집적회로를 보호하기 위한 고전압 펄스 보호 장치에 있어서, 상기 집적회로와 결합된 집적회로 기판 영역; 상기 집적회로 기판 영역과 공통으로 접지에 접속되는 반면에 상기 집적회로 기판 영역으로 부터 분리되는 보호 회로 기판 영역; 및 고전압 펄스로부터 집적회로를 보호하기 위해서, 고전압 펄스를 수신하고 이 고전압 펄스를 최소한 1개 이상의 접속부를 통해 그리고 상기 보호 기판 영역을 통해 공통 접지로 소산시키도록 상기 집적회로와의 최소한 1개 이상의 접속부를 갖고 있으며 상기 보호 회로 기판 영역과 결합된 주 보호 회로를 포함하는 것을 특징으로 하는 고전압 펄스 보호 장치.A high voltage pulse protection device for protecting an integrated circuit from high voltage pulses, comprising: an integrated circuit board region coupled with the integrated circuit; A protective circuit board region connected to ground in common with said integrated circuit board region, said protective circuit board region being separate from said integrated circuit board region; And at least one connection with the integrated circuit to receive a high voltage pulse and dissipate the high voltage pulse through at least one connection and through the protective substrate region to a common ground to protect the integrated circuit from high voltage pulses. And a main protective circuit coupled with said protective circuit board region. 제1항에 있어서, 상기 집적회로 기판 영역이 직접회로 칩을 포함하고 상기 보호 회로 기판 영역이 보호 회로칩을 포함하며, 상기 집적회로 칩 및 상기 보호회로 칩이 분리되어 별개인 것을 특징으로 하는 고전압 펄스 보호 장치.The high voltage of claim 1, wherein the integrated circuit board area includes an integrated circuit chip, the protection circuit board area includes a protection circuit chip, and the integrated circuit chip and the protection circuit chip are separated from each other. Pulse protection device. 제1항에 있어서, 상기 집적회로 기판 영역 및 상기 보호 회로 기판 영역이 단일 칩의 분리 및 별개의 영역들을 포함하는 것을 특징으로 하는 고전압 펄스 보호 장치.2. The high voltage pulse protection device of claim 1, wherein said integrated circuit board region and said protective circuit board region comprise separate and separate regions of a single chip. 제1항에 있어서, 상기 주 보호 회로는 고전압 펄스를 수신하여 이를 상기 보호 회로 기판 영역을 통해 접지로 소산시키기 위한 반도체 정류기를 포함하는 것을 특징으로 하는 고전압 펄스 보호 장치.2. The apparatus of claim 1, wherein the main protection circuit comprises a semiconductor rectifier for receiving a high voltage pulse and dissipating it to ground through the protection circuit board region. 제1항에 있어서, 상기 주 보호 회로는 관련된 부스터 회로를 갖고 있으며, 고전압 펄스를 수신하여 이를 상기 보호 회로 기판 영역으로 소산시키기 위한 반도체 정류기를 포함하는 것을 특징으로 하는 고전압 펄스 보호 장치.2. The high voltage pulse protection device of claim 1, wherein the main protection circuit has an associated booster circuit and includes a semiconductor rectifier for receiving a high voltage pulse and dissipating it to the area of the protection circuit board. 제1항에 있어서, 상기 주 보호 회로는 고전압 펄스를 수신하여 이를 상기 보호 회로 기판 영역을 통해 접지로 소산시키기 위한 게이트 결합 MOSFET를 포함하는 것을 특징으로 하는 고전압 펄스 보호 장치.2. The high voltage pulse protection device of claim 1, wherein the main protection circuit includes a gate coupling MOSFET for receiving a high voltage pulse and dissipating it to ground through the protection circuit board region. 제1항에 있어서, 상기 집적회로 기판 영역이 집적회로 칩을 포함하고 상기 보호 회로 기판 영역은 보호 회로 칩을 포함하며, 보호된 다중-칩 모듈을 형성하기 위해 상기 보호 회로 칩에 접속하기 위한 다수의 상기 집적회로 칩들을 더 포함하는 것을 특징으로 하는 고전압 펄스 보호 장치.2. The integrated circuit board of claim 1, wherein the integrated circuit board region comprises an integrated circuit chip and the protective circuit board region comprises a protective circuit chip, the plurality of connections for connecting to the protective circuit chip to form a protected multi-chip module. And the integrated circuit chips of the high voltage pulse protection device. 고전압 펄스로부터 집적회로를 보호하기 위한 방법에 있어서, 집적회로 기판 영역과 상기 집적회로를 결합시키는 단계; 상기 집적회로 기판 영역을 보호 기판 영역과 함께 공통으로 접지에 접속시키는 반면에 상기 집적회로 기판 영역으로부터 상기 보호 회로 기판 영역을 분리시키는 단계; 및 상기 집적회로가 주 보호 회로와 최소한 1개 이상의 접속부를 갖도록 상기 주 보호 회로를 상기 보호회로 기판 영역과 결합시켜, 상기 최소한 1개 이상의 접속부 및 상기 보호 회로 기판 영역을 통해 고전압 펄스를 상기 공통 접지로 소산시키므로써 상기 고전압 펄스로 부터 집적회로를 보호하는 단계를 더 포함하는 것을 특징으로 하는 집적 회로 보호 방법.CLAIMS 1. A method for protecting an integrated circuit from high voltage pulses, the method comprising: coupling an integrated circuit board region with the integrated circuit; Separating the protective circuit board area from the integrated circuit board area while connecting the integrated circuit board area to ground in common with the protective substrate area; And coupling the main protection circuit with the protection circuit board region such that the integrated circuit has at least one connection with the main protection circuit, thereby causing a high voltage pulse through the at least one connection and the protection circuit board region to the common ground. Protecting the integrated circuit from the high voltage pulse by dissipating 제8항에 있어서, 분리 및 개별 칩들 상에서 상기 집적회로 기판 영역과 상기 보호 회로 기판 영역을 분리시키는 단계를 더 포함하는 것을 특징으로 하는 집적 회로 보호 방법.10. The method of claim 8, further comprising separating and separating the integrated circuit board region and the protective circuit board region on separate chips. 제8항에 있어서, 단일 칩 상의 분리 및 개별 영역들 상에서 상기 집적회로 기판 영역과 상기 보호 회로 기판 영역을 분리시키는 단계를 더 포함하는 것을 특징으로 하는 집적 회로 보호 방법.9. The method of claim 8, further comprising separating the integrated circuit board area and the protective circuit board area on separate and discrete areas on a single chip. 제8항에 있어서, 반도체 정류기 내에서 고전압 펄스를 수신하고 이를 상기 보호 회로 기판 영역을 통해 접지로 소산시키는 단계를 더 포함하는 것을 특징으로 하는 집적 회로 보호 방법.10. The method of claim 8, further comprising receiving a high voltage pulse in a semiconductor rectifier and dissipating it to ground through the protective circuit board region. 제8항에 있어서, 관련된 부스터 회로를 갖고 있는 주 보호 회로 내에서 고전압 펄스를 수신하고 이를 상기 보호 회로 기판 영역을 통해 접지로 소산시키는 단계를 더 포함하는 것을 특징으로 하는 집적 회로 보호 방법.9. The method of claim 8, further comprising receiving a high voltage pulse in a main protection circuit having an associated booster circuit and dissipating it to ground through the protection circuit board area. 제8항에 있어서, 게이트-결합 MOSFET를 갖고 있는 주 보호 회로 내에서 고전압 펄스를 수신하고 이를 상기 보호 회로 기판 영역을 통해 접지로 소산시키는 단계를 더 포함하는 것을 특징으로 하는 집적 회로 보호 방법.10. The method of claim 8, further comprising receiving a high voltage pulse in a main protection circuit having a gate-coupled MOSFET and dissipating it to ground through the protection circuit board region. 제8항에 있어서, 상기 집적회로 기판 영역이 집적회로 칩을 포함하고 상기 보호 회로 기판 영역은 보호 회로 칩을 포함하며, 또한 보호되는 다중-칩 모듈을 형성하기 위해 상기 보호 회로 칩에 다수의 상기 집적회로 칩들을 접속시키는 단계들을 더 포함하는 것을 특징으로 하는 집적회로 보호 방법.10. The apparatus of claim 8, wherein the integrated circuit board region comprises an integrated circuit chip and the protective circuit board region comprises a protective circuit chip, and wherein the plurality of the protection circuit chips are formed on the protective circuit chip to form a protected multi-chip module. And connecting the integrated circuit chips. 고전압 펄스로부터 집적회로를 보호하기 위해 고전압 펄스 보호 장치를 형성하는 방법에 있어서, 상기 집적회로와 결합된 집적회로 기판 영역을 형성하는 단계; 상기 집적회로 기판 영역과 함께 공통으로 접지에 접속되는 반면에 상기 집적회로 기판 영역으로부터 분리되는 보호 회로 기판 영역을 형성하는 단계; 및 고전압 펄스로부터 집적회로를 보호하기 위해서, 고전압 펄스를 수신하고 이를 최소한 1개 이상의 접속부를 통해 그리고 상기 보호회로 기판 영역을 통해 상기 공통 접지로 소산시키도록 상기 집적회로와 최소한 1개 이상의 접속부를 갖고 있으며 상기 보호 회로 기판 영역과 결합된 주 보호 회로를 형성하는 단계를 더 포함하는 것을 특징으로 하는 고전압 펄스 보호 장치 형성 방법.CLAIMS 1. A method of forming a high voltage pulse protection device to protect an integrated circuit from high voltage pulses, the method comprising: forming an integrated circuit substrate region coupled with the integrated circuit; Forming a protective circuit board region in common with the integrated circuit board region, the protective circuit board region being separated from the integrated circuit board region; And at least one connection with the integrated circuit to receive a high voltage pulse and dissipate it to the common ground through at least one connection and through the protection circuit board region to protect the integrated circuit from high voltage pulses. And forming a main protection circuit coupled with the protection circuit board area. 제15항에 있어서, 상기 집적회로 기판 영역과 상기 보호 회로 기판 영역이 분리되어 서로 구별되도록, 집적회로 칩을 포함하는 상기 집적회로 기판 영역을 형성하고 보호 회로 칩을 포함하는 상기 보호 회로 기판 영역을 형성하는 단계들을 더 포함하는 것을 특징으로 하는 고전압 펄스 보호 장치 형성 방법.The protective circuit board area of claim 15, wherein the integrated circuit board area including the integrated circuit chip is formed and the protective circuit board area includes the protection circuit chip such that the integrated circuit board area and the protection circuit board area are separated from each other. And forming the high voltage pulse protection device. 제15항에 있어서, 상기 집적회로 기판 영역과 상기 보호 회로 기판 영역을 단일 칩의 분리 및 별개의 영역들로 형성하는 단계들을 더 포함하는 것을 특징으로 하는 고전압 펄스 보호 장치 형성 방법.16. The method of claim 15, further comprising forming the integrated circuit board region and the protective circuit board region into separate and separate regions of a single chip. 제15항에 있어서, 고전압 펄스를 수신하여 이를 상기 보호 회로 기판 영역을 통해 접지로 소산시키기 위해 반도체 정류기를 포함하는 상기 주 보호 회로를 형성하는 단계를 더 포함하는 것을 특징으로 하는 고전압 펄스 보호 장치 형성 방법.16. The apparatus of claim 15, further comprising forming the main protection circuit including a semiconductor rectifier to receive a high voltage pulse and dissipate it to ground through the protection circuit board region. Way. 제15항에 있어서, 고전압 펄스를 수신하여 이를 상기 보호 회로 기판 영역을 통해 접지로 소산시키기 위해, 주 보호 회로 트리거 전압을 감소시키기 위한 관련부스터 회로를 갖춘 반도체 정류기를 구비하는 상기 주 보호 회로를 형성하는 단계를 더 포함하는 것을 특징으로 하는 고전압 펄스 보호 장치 형성 방법.16. The method of claim 15, wherein the main protection circuit is provided with a semiconductor rectifier with an associated booster circuit for reducing a main protection circuit trigger voltage to receive a high voltage pulse and dissipate it to ground through the protection circuit board area. And forming a high voltage pulse protection device. 제15항에 있어서, 고전압 펄스를 수신하여 이를 상기 보호 회로 기판 영역을 통해 접지로 소산시키기 위해, 게이트-결합 MOSFET를 구비하는 상기 주 보호 회로를 형성하는 단계를 더 포함하는 것을 특징으로 하는 고전압 펄스 보호 장치 형성 방법.16. The high voltage pulse of claim 15, further comprising forming the main protection circuit having a gate-coupled MOSFET to receive a high voltage pulse and dissipate it to ground through the protection circuit board area. How to form a protective device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940022903A 1993-09-13 1994-09-12 Methods and systems for protecting integrated circuits from various electrical transients KR100331661B1 (en)

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