JP2001094053A5 - Semiconductor chips and liquid crystal display devices - Google Patents
Semiconductor chips and liquid crystal display devices Download PDFInfo
- Publication number
- JP2001094053A5 JP2001094053A5 JP1999268031A JP26803199A JP2001094053A5 JP 2001094053 A5 JP2001094053 A5 JP 2001094053A5 JP 1999268031 A JP1999268031 A JP 1999268031A JP 26803199 A JP26803199 A JP 26803199A JP 2001094053 A5 JP2001094053 A5 JP 2001094053A5
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- JP
- Japan
- Prior art keywords
- semiconductor chip
- terminal
- dummy
- wiring
- liquid crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 239000004065 semiconductor Substances 0.000 title claims 23
- 239000004973 liquid crystal related substance Substances 0.000 title claims 7
- 239000000758 substrate Substances 0.000 claims 5
- 230000015556 catabolic process Effects 0.000 claims 2
- 230000001681 protective Effects 0.000 claims 1
Claims (12)
前記半導体チップの内部回路に接続されないダミー端子と、
前記ダミー端子を静電破壊から守る保護手段とを有する半導体チップ。In the semiconductor chip that drives the electrodes of the liquid crystal panel,
Dummy terminals not connected to the internal circuit of the semiconductor chip;
A semiconductor chip having protection means for protecting the dummy terminals from electrostatic breakdown.
第１電位を受ける第１端子と、
前記第１電位よりも低い第２電位を受ける第２端子とを有し、
前記保護手段は、一端を前記第１端子に接続され、他端を前記ダミー端子に接続される第１保護手段と、一端を前記第２端子に接続され、他端を前記ダミー端子に接続される第２保護手段とからなり、
前記保護手段は、ＰＮ接合により形成されるダイオードである半導体チップ。In claim 1,
A first terminal for receiving a first potential;
A second terminal that receives a second potential lower than the first potential;
The protection means has one end connected to the first terminal, the other end connected to the dummy terminal, one end connected to the second terminal, and the other end connected to the dummy terminal. Second protective means,
The protection means is a semiconductor chip which is a diode formed by a PN junction.
前記液晶パネルの電極に印加する電圧を出力する出力端子をさらに有し、
前記出力端子は、前記半導体チップの外部の配線と前記ダミー端子とを介して前記液晶パネルの電極と接続される半導体チップ。In claim 1 or claim 2,
An output terminal that outputs a voltage applied to the electrode of the liquid crystal panel;
The output terminal is a semiconductor chip connected to an electrode of the liquid crystal panel via a wiring outside the semiconductor chip and the dummy terminal.
マイクロコンピュータより送信される信号を受ける入力端子をさらに有し、
前記入力端子は、前記半導体チップの外部の配線と前記ダミー端子とを介して前記マイクロコンピュータが配設される基板上の配線と接続される半導体チップ。In claim 1 or claim 2,
An input terminal for receiving a signal transmitted from the microcomputer;
The input terminal is a semiconductor chip connected to a wiring on a substrate on which the microcomputer is arranged via a wiring outside the semiconductor chip and the dummy terminal.
前記ダミー端子を複数有し、
前記複数のダミー端子は、前記半導体チップの第１辺に、前記第１辺が延在する第１方向に沿って配置され、
前記複数のダミー端子のそれぞれに接続される前記第１保護手段と前記第２保護手段とは、接続されるダミー端子を挟んで前記第１方向と交差する方向に配列される半導体チップ。In claim 2,
A plurality of dummy terminals;
The plurality of dummy terminals are arranged on a first side of the semiconductor chip along a first direction in which the first side extends,
The first protection means and the second protection means connected to each of the plurality of dummy terminals are semiconductor chips arranged in a direction intersecting the first direction with the connected dummy terminals interposed therebetween.
前記半導体チップは、フェイスダウンで実装される半導体チップ。In claims 1 to 5,
The semiconductor chip is a semiconductor chip mounted face down.
前記液晶パネルを構成する基板と、
前記基板上に形成される配線とを有し、
前記配線は、前記半導体チップと前記基板との間に配置される液晶表示装置。A semiconductor chip according to claim 1;
A substrate constituting the liquid crystal panel;
Wiring formed on the substrate,
The wiring is a liquid crystal display device disposed between the semiconductor chip and the substrate.
前記半導体チップが搭載される基板には、前記半導体チップの端子が配置される領域の内側を通過する配線が形成され、前記ダミー端子は前記配線と接する位置に配置される半導体チップ。A semiconductor chip including an output terminal disposed along a first side, an input terminal disposed along a second side opposite to the first side, and a dummy terminal not connected to an internal circuit;
The substrate on which the semiconductor chip is mounted is formed with a wiring passing through the inside of a region where the terminal of the semiconductor chip is disposed, and the dummy terminal is disposed at a position in contact with the wiring.
前記出力端子は、前記配線と接する位置に配置される半導体チップ。In claim 8,
The output terminal is a semiconductor chip disposed at a position in contact with the wiring.
前記入力端子は、前記配線と接する位置に配置される半導体チップ。In claim 8,
The input terminal is a semiconductor chip disposed at a position in contact with the wiring.
前記ダミー端子は、前記半導体チップ上に形成され前記ダミー端子を静電破壊から守る保護手段と接続される半導体チップ。In claims 8 to 10,
The dummy terminal is a semiconductor chip formed on the semiconductor chip and connected to protection means for protecting the dummy terminal from electrostatic breakdown.
前記出力端子は、液晶パネルの電極に印加する電圧を出力する半導体チップ。In claims 8 to 11,
The output terminal is a semiconductor chip that outputs a voltage applied to an electrode of a liquid crystal panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26803199A JP4034915B2 (en) | 1999-09-22 | 1999-09-22 | Semiconductor chip and liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26803199A JP4034915B2 (en) | 1999-09-22 | 1999-09-22 | Semiconductor chip and liquid crystal display device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007250357A Division JP4614244B2 (en) | 2007-09-27 | 2007-09-27 | Semiconductor device for liquid crystal display |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2001094053A JP2001094053A (en) | 2001-04-06 |
| JP2001094053A5 true JP2001094053A5 (en) | 2005-06-30 |
| JP4034915B2 JP4034915B2 (en) | 2008-01-16 |
Family
ID=17452929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26803199A Expired - Fee Related JP4034915B2 (en) | 1999-09-22 | 1999-09-22 | Semiconductor chip and liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4034915B2 (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3744450B2 (en) | 2001-05-09 | 2006-02-08 | セイコーエプソン株式会社 | Electro-optical device, driving IC and electronic device |
| TWI302625B (en) | 2003-06-26 | 2008-11-01 | Au Optronics Corp | Polysilicon thin film transistor liquid crystal display having a plurality of common voltage drivers |
| KR101022278B1 (en) * | 2003-12-15 | 2011-03-21 | 삼성전자주식회사 | Driving chip and display apparatus having the same |
| KR101051013B1 (en) * | 2003-12-16 | 2011-07-21 | 삼성전자주식회사 | Driving chip and display device having same |
| JP4561145B2 (en) * | 2004-03-29 | 2010-10-13 | カシオ計算機株式会社 | Display control apparatus and display control method |
| JP2006106132A (en) * | 2004-09-30 | 2006-04-20 | Sharp Corp | Display driving circuit and display device |
| KR100685412B1 (en) | 2004-11-04 | 2007-02-22 | 삼성에스디아이 주식회사 | Printed Circuit Board and Flexible Printed Circuit Board having redundant wire or pad |
| JP4274108B2 (en) * | 2004-11-12 | 2009-06-03 | セイコーエプソン株式会社 | Electro-optical device and electronic apparatus |
| KR20060104088A (en) * | 2005-03-29 | 2006-10-09 | 삼성전자주식회사 | Circuit board for display device and display device including the same |
| JP2007012938A (en) * | 2005-06-30 | 2007-01-18 | Seiko Epson Corp | Integrated circuit device |
| JP4910319B2 (en) * | 2005-07-06 | 2012-04-04 | セイコーエプソン株式会社 | Integrated circuit device and electronic device incorporating interface circuit |
| JP4946000B2 (en) * | 2005-10-24 | 2012-06-06 | セイコーエプソン株式会社 | Integrated circuit device and electronic apparatus |
| JP4945998B2 (en) * | 2005-10-24 | 2012-06-06 | セイコーエプソン株式会社 | Integrated circuit device and electronic apparatus |
| JP4945999B2 (en) * | 2005-10-24 | 2012-06-06 | セイコーエプソン株式会社 | Integrated circuit device and electronic apparatus |
| JP4820683B2 (en) * | 2006-04-28 | 2011-11-24 | 川崎マイクロエレクトロニクス株式会社 | Semiconductor device and method for preventing breakdown of semiconductor device |
| JP5405283B2 (en) * | 2009-12-10 | 2014-02-05 | シャープ株式会社 | Semiconductor device and power supply method thereof |
-
1999
- 1999-09-22 JP JP26803199A patent/JP4034915B2/en not_active Expired - Fee Related
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