JP4945998B2 - Integrated circuit device and electronic apparatus - Google Patents

Description

  The present invention relates to an integrated circuit device and an electronic apparatus.

  In recent years, high-speed serial transfer such as LVDS (Low Voltage Differential Signaling) has attracted attention as an interface for the purpose of reducing EMI noise. In this high-speed serial transfer, the transmitter circuit transmits serialized data as a differential signal, and the receiver circuit differentially amplifies the differential signal to realize data transfer.

  A general mobile phone includes a first device portion provided with buttons for inputting a telephone number and characters, a second device portion provided with an LCD (Liquid Crystal Display) and a camera device, and first and first devices. It is comprised by connection parts, such as a hinge which connects two apparatus parts. Therefore, data transfer between the first circuit board provided in the first device portion and the second circuit board provided in the second device portion is performed by high-speed serial transfer using a small amplitude differential signal. This is advantageous because the number of wires passing through the connection portion can be reduced.

  In order to realize such high-speed serial transfer, it is necessary to incorporate a high-speed interface circuit into an integrated circuit device such as a display driver or a host device. When such a high-speed interface circuit is incorporated, the transistors in the high-speed interface circuit may be destroyed by static electricity.

Further, since the differential signal of the high-speed interface circuit has a small voltage amplitude such as 0.1 V to 1.0 V, it is easily affected by noise generated in other circuit blocks such as a driver circuit. In addition, noise generated in the high-speed interface circuit may adversely affect the driver circuit.
JP 2001-222249 A

  The present invention has been made in view of the above technical problems, and an object of the present invention is to provide an integrated circuit device capable of effectively preventing electrostatic breakdown and the like and an electronic apparatus including the integrated circuit device. is there.

  The present invention includes a high-speed interface circuit block including a physical layer circuit that performs data transfer via a serial bus, and at least one other circuit block. The high-speed interface circuit block includes a power source for the high-speed interface circuit block, Including first and second protection circuit blocks including a protection circuit provided between the power supply of the other circuit block, and the first protection circuit block is a first side that is a short side of the high-speed interface circuit block. The second protection circuit block is related to an integrated circuit device arranged on the third side opposite to the first side of the high-speed interface circuit block.

  According to the present invention, the first protection circuit block is disposed on the first side of the high-speed interface circuit block, and the second protection circuit block is disposed on the second side. Therefore, when static electricity from the power source of another circuit block comes from the first side, the first protection circuit block can prevent electrostatic breakdown or the like, and static electricity from the power source of the other circuit block is second. In the case of coming from the side, the electrostatic breakdown or the like can be prevented by the second protection circuit block. Therefore, even when a high-speed interface circuit is incorporated, electrostatic breakdown and the like can be effectively prevented, and the reliability of the integrated circuit device can be improved.

  In the present invention, the physical layer circuit may be disposed between the first and second protection circuit blocks.

  By doing so, it is possible to effectively prevent the transistors of the physical layer circuit from being destroyed by the first and second protection circuit blocks arranged on both sides of the physical layer circuit.

  In the present invention, the high-speed interface circuit block includes the physical layer circuit and a logic circuit, and a direction from the first side to the third side of the high-speed interface circuit block is a first direction. When the direction from the second side, which is the long side of the high-speed interface circuit block, to the fourth side facing the second direction is the second direction, the logic circuit is configured to output the second layer of the physical layer circuit. It may be arranged on the direction side.

  In this way, an efficient layout along the signal flow becomes possible.

  In the present invention, the other circuit block includes a driver logic circuit block that generates a display control signal, and the driver logic circuit block is arranged on the second direction side of the logic circuit. May be.

  In this way, the wiring between the logic circuit and the driver logic circuit block can be connected by a short path, and the layout efficiency can be improved.

  In the present invention, when the length of the physical layer circuit in the first direction is L1, and the length of the logic circuit in the first direction is L2, L2> L1 Good.

  In this way, the width of the signal wiring area between the logic circuit and the driver logic circuit block can be widened, and the wiring can be connected by a short path.

  In the present invention, when the direction opposite to the first direction is the third direction, the first protection circuit block is arranged in the first region on the third direction side of the physical layer circuit. The second protection circuit block may be arranged in a second region on the first direction side of the physical layer circuit.

  In this way, it is possible to effectively utilize the first area that is the empty area on the third direction side of the physical layer circuit and the second area that is the empty area on the first direction side.

  In the present invention, a capacitor region in which a capacitor provided between the high potential side power source and the low potential side power source of the high-speed interface circuit block is disposed in the first and second regions. Good.

  In this way, the power supply can be stabilized by effectively utilizing the first and second regions.

  In the present invention, the high-speed interface circuit block includes the physical layer circuit, a logic circuit, and a power supply line of a shared power supply, and the first protection circuit block includes a power supply of the physical layer circuit and the shared power supply. A first protection circuit provided between the power supply of the logic circuit and the shared power supply, a second protection circuit provided between the power supply of the logic circuit and the shared power supply. The second protection circuit block includes a fourth protection circuit provided between a power supply of the physical layer circuit and the shared power supply, a power supply of the logic circuit, and the shared power supply. And a sixth protection circuit provided between the power supply of the other circuit block and the shared power supply.

  In this way, a one-stage protection circuit is arranged between the power supply for the physical layer circuit, the power supply for the logic circuit, the power supply for other circuit blocks, and the shared power supply. Accordingly, it is possible to prevent a situation where the electrostatic withstand voltage and noise resistance are reduced only in a part of the paths.

  In the present invention, the high-speed interface circuit block includes the physical layer circuit and a logic circuit, and the first protection circuit block is between a power supply of the physical layer circuit and a power supply of the other circuit block. A first protection circuit provided; and a second protection circuit provided between a power supply of the logic circuit and a power supply of the other circuit block, wherein the second protection circuit block includes: A fourth protection circuit provided between a power supply and the power supply of the other circuit block; and a fifth protection circuit provided between the power supply of the logic circuit and the power supply of the other circuit block. Good.

  In this way, a one-stage protection circuit is arranged between the power supply for the physical layer circuit, the power supply for the logic circuit, and the power supply for other circuit blocks. Therefore, it is possible to prevent a situation where the electrostatic withstand voltage or the like is lowered only in a part of the paths.

  In the present invention, when the direction from the first side to the third side of the high-speed interface circuit block is a first direction, and the direction opposite to the first direction is a third direction. The second protection circuit is disposed on the third direction side of the first protection circuit, and the fifth protection circuit is disposed on the first direction side of the fourth protection circuit. It may be.

  In this way, it is possible to efficiently wire the power supply lines of the power supplied to the physical layer circuit and the logic circuit.

  In the present invention, the second power supply for connecting the second protection circuit and the logic circuit to the third direction side of the first power supply line for connecting the first protection circuit and the physical layer circuit. A fifth power supply for connecting the fifth protection circuit and the logic circuit to the first direction side of the fourth power supply line for connecting the fourth protection circuit and the physical layer circuit. Lines may be routed.

  In this way, it is possible to prevent the first and second power supply lines from being crossed and the fourth and fifth power supply lines from crossing and to prevent layout efficiency.

  In the present invention, the direction from the second side, which is the long side of the high-speed interface circuit block, to the fourth side facing the second side is defined as the second direction, and the direction opposite to the second direction is defined as the fourth direction. In this case, the first pad to which the first power supply line is connected is disposed on the fourth direction side of the first protection circuit, and the second pad to which the second power supply line is connected. Are arranged on the third direction side of the first pad, and the fourth pad to which the fourth power supply line is connected is on the fourth direction side of the fourth protection circuit. A fifth pad that is disposed and connected to the fifth power supply line may be disposed on the first direction side of the fourth pad.

  In this way, the first and second power lines from the first and second pads and the fourth and fifth power lines from the fourth and fifth pads are connected to both sides of the physical layer circuit. This makes it possible to efficiently perform wiring by using the free space, thereby improving the layout efficiency.

  In the present invention, at least one of the reception pad and the transmission pad of the physical layer circuit may be disposed between the first pad and the fourth pad.

  In this way, the receiving and transmitting pads of the physical layer circuit can be arranged together near the center of the high-speed interface circuit block, which can improve the signal transmission quality and the efficient layout of the pads. It becomes possible.

  In the present invention, the protection circuit included in the first and second protection circuit blocks may include a bidirectional diode.

  In this way, the protection circuits of the first and second protection circuit blocks can be provided with an antistatic function and a noise removal function.

  The present invention also relates to an electronic apparatus including any one of the integrated circuit devices described above and a display panel driven by the integrated circuit device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Circuit Configuration of Integrated Circuit Device FIG. 1 shows a circuit configuration example when the integrated circuit device 10 of this embodiment is a display driver. The circuit configuration of the integrated circuit device 10 is not limited to that shown in FIG. 1, and various modifications can be made. For example, some of the components in FIG. 1 may be omitted, or components other than those shown in FIG. 1 may be included. The integrated circuit device according to the present embodiment is not limited to the display driver, and may be a host device such as a baseband engine, an application processor, or an image processing controller.

  The display panel 512 includes a plurality of data lines (source lines), a plurality of scanning lines (gate lines), and a plurality of pixels specified by the data lines and the scanning lines. A display operation is realized by changing the optical characteristics of the electro-optical element (in a narrow sense, a liquid crystal element) in each pixel region. This display panel 512 can be constituted by an active matrix type panel using switching elements such as TFT and TFD. Note that the display panel 512 may be a panel other than the active matrix method, or may be a panel other than the liquid crystal panel (such as an organic EL panel).

  A memory 520 (RAM) stores image data. The memory cell array 522 includes a plurality of memory cells and stores image data (display data) for at least one frame (one screen). The memory 520 includes a row address decoder 524 (MPU / LCD row address decoder), a column address decoder 526 (MPU column address decoder), and a write / read circuit 528 (MPU write / read circuit).

  The logic circuit 540 (driver logic circuit) generates a display control signal for controlling display timing and data processing timing. The logic circuit 540 can be formed by automatic placement and routing such as a gate array (G / A). The control circuit 542 generates various control signals and controls the entire apparatus. The display timing control circuit 544 generates a display timing control signal and controls reading of image data from the memory 520 to the display panel 512 side. The host I / F (interface) circuit 546 implements a host interface that generates an internal pulse for each access from the host (MPU) and accesses the memory 520. The RGB I / F circuit 548 realizes an RGB interface that writes moving image RGB data to the memory 520 using a dot clock. The high-speed I / F circuit 620 realizes high-speed serial transfer via a serial bus.

  The data driver 550 generates a data signal for driving the data lines of the display panel 512. Specifically, the data driver 550 receives gradation data that is image data from the memory 520 and receives a plurality of (for example, 64 levels) gradation voltages (reference voltages) from the gradation voltage generation circuit 610. Then, a voltage corresponding to the gradation data is selected from the plurality of gradation voltages and is output to each data line of the display panel 512 as a data signal (data voltage).

  The scan driver 570 generates a scan signal for driving the scan line of the display panel. The power supply circuit 590 generates various power supply voltages and supplies them to the data driver 550, the scan driver 570, the gradation voltage generation circuit 610, and the like. The gradation voltage generation circuit 610 (γ correction circuit) generates a gradation voltage and outputs it to the data driver 550.

2. Configuration of High-Speed I / F Circuit FIG. 2A shows a configuration example of a high-speed I / F (interface) circuit 620. The physical layer circuit 630 (analog front-end circuit, transceiver) receives data (packets) via a serial bus using differential signals (differential data signals, differential strobe signals, differential clock signals), etc. , A circuit for transmitting. Specifically, data transmission / reception is performed by current driving or voltage driving the differential signal line of the serial bus. The physical layer circuit 630 can include at least one of a receiver circuit that receives data via a serial bus and a transmitter circuit that transmits data via a serial bus.

  The serial bus may have a multi-channel configuration. Serial transfer may be performed by single-ended transfer. The physical layer circuit 630 can include a high-speed logic circuit. This high-speed logic circuit is a circuit that operates with a high-speed clock corresponding to the transfer clock of the serial bus. Specifically, the physical layer circuit 630 is a serial / parallel conversion circuit that converts serial data received via the serial bus into parallel data, and parallel / serial conversion that converts parallel data into serial data transmitted via the serial bus. A circuit, a FIFO, an elasticity buffer, a frequency divider, or the like can be included.

  The logic circuit 650 is a logic circuit built in the high-speed I / F circuit 620, and performs processing of a link layer and a transaction layer that are upper layers of the physical layer. For example, the packet received by the physical layer circuit 630 via the serial bus is analyzed, the packet header and data are separated, and the header is extracted. In addition, when a packet is transmitted via the serial bus, the packet generation process is performed. The logic circuit 650 can be formed by automatic placement and routing such as a gate array (G / A).

  The logic circuit 650 includes a driver I / F circuit 672. The driver I / F circuit 672 performs interface processing between the high-speed I / F circuit 620 and the internal circuit (driver logic circuit 540 and host I / F circuit 546 in FIG. 1) of the display driver. Specifically, the driver I / F circuit 672 generates interface signals including an address 0 signal A0 (command / data identification signal), a write signal WR, a read signal RD, a parallel data signal PDATA, a chip select signal CS, and the like. And output to the internal circuit (other circuit block) of the display driver.

  FIG. 2B shows a configuration example of the physical layer circuit. In FIG. 2B, the physical layer circuit 640 is built in the host device, and the physical layer circuit 630 is built in the display driver. Reference numerals 636, 642, and 644 denote transmitter circuits, and reference numerals 632, 634, and 646 denote receiver circuits. Reference numerals 638 and 648 denote wakeup detection circuits. The transmitter circuit 642 on the host side drives STB +/−. The client-side receiver circuit 632 amplifies the voltage generated at both ends of the resistor RT1 by driving, and outputs a strobe signal STB_C to a subsequent circuit. The host-side transmitter circuit 644 drives DATA +/−. The client-side receiver circuit 634 amplifies the voltage generated at both ends of the resistor RT2 by driving, and outputs the data signal DATA_C_HC to the subsequent circuit.

  As shown in FIG. 2C, the transmitting side generates a strobe signal STB by taking the exclusive OR of the data signal DATA and the clock signal CLK, and transmits this STB to the receiving side via the high-speed serial bus. To do. The receiving side reproduces the clock signal CLK by taking an exclusive OR of the received data signal DATA and the strobe signal STB.

  Note that the configuration of the physical layer circuit is not limited to that shown in FIG. 2B, and various modifications such as those shown in FIGS. 3A and 3B are possible.

  For example, in the first modification of FIG. 3A, the host side outputs a differential data signal (OUT data) DTO +/− in synchronization with the edge of the differential clock signal CLK +/−. Therefore, the target side can sample and capture DTO +/− using CLK +/−. The target side generates and outputs a differential strobe signal STB +/− based on the differential clock signal CLK +/− supplied from the host side. The target side outputs a differential data signal (IN data) DTI +/− in synchronization with the edge of STB +/−. Therefore, the host side can sample and capture DTI +/− using STB +/−.

  In the second modification of FIG. 3B, the data receiver circuit 750 receives the differential data signal DATA +/−, and outputs the obtained serial data SDATA to the serial / parallel conversion circuit 754. The clock receiver circuit 752 receives the differential clock signal CLK +/−, and outputs the obtained clock CLK to a PLL (Phase Locked Loop) circuit 756 in the subsequent stage. The PLL circuit 756 generates a sampling clock SCK (a multi-phase sampling clock having the same frequency and different phases) based on the clock CLK, and outputs the sampling clock SCK to the serial / parallel conversion circuit 754. The serial / parallel conversion circuit 754 samples the serial data SDATA using the sampling clock SCK and outputs parallel data PDATA.

  For example, in a cellular phone, a host device such as an MPU, BBE / APP, or image processing controller is mounted on a first circuit board of a first device portion of the cellular phone provided with buttons for entering a telephone number and characters. Is done. The display driver is mounted on the second circuit board of the second device portion of the mobile phone provided with a display panel (LCD) and a camera device.

  Conventionally, data transfer between the host device and the display driver has been realized by parallel transfer at the CMOS voltage level. For this reason, the number of wirings that pass through a connecting portion such as a hinge connecting the first and second device portions increases, which causes problems such as hindering the degree of freedom in design and generating EMI noise.

  On the other hand, in FIGS. 2A to 3B, data transfer between the host device and the display driver is realized by small amplitude serial transfer. Therefore, it is possible to reduce the number of wires passing through the connecting portions of the first and second device portions, and to reduce the generation of EMI noise.

3. Protection Circuit Block FIG. 4 shows a layout example of the integrated circuit device 10. The integrated circuit device 10 includes a high-speed I / F circuit block HB and at least one other circuit block (circuit block other than HB). Here, the other circuit blocks are data driver blocks. Alternatively, they are a logic circuit block for driver (display driver), a power supply circuit block, and a gradation voltage generation circuit block. Alternatively, it is a memory block in the case of a built-in memory, and a scan driver block in the case of an amorphous TFT.

  The high-speed I / F circuit block HB includes first and second protection circuit blocks (protection circuit regions) PTB1 and PTB2. Each of the protection circuit blocks PTB1 and PTB2 is provided between the power source (low potential power source) VSSM, VSSG, or VSSA of the high-speed I / F circuit block HB and the power source (low potential power source) VSS of the other circuit block. At least one protection circuit is included.

  The protection circuit block PTB1 is arranged on the first side SE1 side of the high-speed I / F circuit block HB, and the protection circuit block PTB2 is arranged on the third side SE3 side facing the side SE1 of the HB. That is, PTB1 and PTB2 are arranged on both sides of the HB. For example, in FIG. 4, the direction from the first side SE1 which is the short side of the high-speed I / F circuit block HB to the third side SE3 facing the first direction D1 is the first direction D1, and the opposite direction of D1 is the third direction. It is assumed that the direction is D3. A direction from the second side SE2 which is the long side of HB to the fourth side SE4 facing the second side SE2 is defined as a second direction D2, and a direction opposite to D2 is defined as a fourth direction D4. Assuming a center line along the D2 direction of the high-speed I / F circuit block HB, the protection circuit block PTB1 is disposed on the D3 direction side of the center line, and the protection circuit block PTB2 is disposed on the D1 direction side of the center line. Is done. In FIG. 4, the left side of HB is the first side SE1 and the right side is the third side SE3, but the left side may be the third side SE3 and the right side may be the first side SE1.

  According to the arrangement of FIG. 4, when an electrostatic voltage is applied between different power sources, it is possible to effectively prevent electrostatic breakdown of transistors and the like in the high-speed I / F circuit block HB. For example, when an electrostatic voltage is applied between the driver power supply VSS and the HB power supply VSSM or VSSG, the protection circuits (bidirectional diodes, etc.) of PTB1 and PTB2 serve as a static electricity discharge path. ESD damage is prevented.

  In particular, the high-speed I / F circuit block HB is an elongated block having a long length in the D1 direction. Therefore, if the protection circuit block is disposed near the center of the HB, the transistor in the HB may be destroyed before electrostatic discharge is performed by the protection circuit.

  In this regard, in FIG. 4, the protection circuit blocks PTB1 and PTB2 are arranged on both sides of the high-speed I / F circuit block HB. Accordingly, it is possible to discharge static electricity from VSS at the entrance portions that are positions on both sides of the HB, so that it is possible to effectively prevent the transistor in the HB from being electrostatically destroyed.

  Note that each of the protection circuit blocks PTB1 and PTB2 may include at least one protection circuit between different types of power supplies (VSSM, VSSG, VSSA, VSS). Further, these protection circuits may be arranged in a nearby place or may be arranged in a remote place.

  In addition to the function as an electrostatic protection element, the protection circuit of PTB1 and PTB2 may have a function as a noise removal element that prevents noise transmission from VSS. That is, the physical layer circuit of the high-speed I / F circuit block HB is composed of an analog circuit, and performs data transfer with a differential signal having a small amplitude, for example. Accordingly, the operation of the analog circuit of the physical layer circuit is adversely affected by noise from the internal circuit (driver logic circuit or the like) of the display driver, and the transmission quality may be deteriorated. Conversely, since the physical layer circuit performs data transfer at a high transfer rate such as 100 to 500 Mbps, noise generated by the physical layer circuit may adversely affect the operation of the internal circuit of the display driver. . If the protection circuit of PTB1 and PTB2 has a function of a noise removing element, such an adverse effect of noise can be prevented.

  In the high-speed I / F circuit, impedance matching is performed between the transmission side and the reception side in order to prevent signal reflection. However, when the integrated circuit device is mounted on a glass substrate by COG (Chip On Glass), the contact resistance at the bumps at both ends of the integrated circuit device increases. That is, the thermal expansion coefficients of the integrated circuit device and the glass substrate are different. Therefore, the stress (thermal stress) caused by the difference in thermal expansion coefficient is larger at both ends of the integrated circuit device than at the center. For this reason, the contact resistance at the bumps increases with time at both ends. Therefore, if pads connected to bumps at both ends of the integrated circuit device are used as reception pads or transmission pads (DATA +/−, etc.) of a high-speed I / F circuit, impedance matching occurs due to an increase in contact resistance at the bumps. Collapses and the signal quality of high-speed serial transfer deteriorates.

  In this regard, in FIG. 4, the high-speed I / F circuit block HB is disposed near the center excluding both ends of the integrated circuit device 10. Specifically, other circuit blocks other than HB are arranged between the side SD1 of the integrated circuit device 10 and the high-speed I / F circuit block HB (side SE1 of HB). Further, a circuit block other than HB is arranged between the side SD3 and the HB (HB side SE3) of the integrated circuit device 10. In this way, the high-speed I / F circuit block HB is not disposed at both ends of the integrated circuit device 10. Therefore, impedance mismatch caused by an increase in contact resistance can be reduced, and deterioration in signal quality of high-speed serial transfer can be reduced.

4). Detailed Layout Example of Integrated Circuit Device and High-Speed I / F Circuit Block FIG. 5 shows a detailed layout example of the integrated circuit device 10 and the high-speed I / F circuit block HB. In FIG. 5, the physical layer circuit PHY included in the HB is arranged between the protection circuit blocks PTB1 and PTB2. That is, PTB1 is arranged on the PHY D3 direction side, and PTB2 is arranged on the PHY D1 direction side. In this way, it is possible to effectively prevent static electricity from the power source VSS from being discharged by the protection circuits of the PTB1 and PTB2 on both sides of the HB and destroying the transistor of the physical layer circuit PHY between the PTB1 and PTB2. it can. Further, it is possible to effectively prevent noise from the power source VSS from being transmitted to the physical layer circuit PHY. A modification in which PTB1 and PTB2 are not arranged on both sides of the physical layer circuit PHY is also possible. For example, PTB1 and PTB2 may be arranged on both sides of the logic circuit HL.

  As shown in FIG. 5, the high-speed I / F circuit block HB includes a physical layer circuit PHY and a logic circuit HL (650 in FIG. 2A). The logic circuit HL is a circuit that performs link layer and transaction layer processing and interface processing with a driver circuit. Then, the logic circuit HL is arranged on the D2 direction side (direction side from the side SE2 to SE4) of the physical layer circuit PHY. Furthermore, the integrated circuit device 10 includes a driver logic circuit block LB (540 in FIG. 1) that generates a display control signal as a circuit block other than the high-speed I / F circuit block HB. The driver logic circuit block LB is disposed on the D2 direction side of the logic circuit HL.

  In FIG. 5, the physical layer circuit PHY receives serial data (image data) from the host device, converts it into parallel data, and outputs it to the logic circuit HL. The logic circuit HL generates a host interface signal (A0, WR, RD, PDATA, etc.) as shown in FIG. 2A and outputs it to the driver logic circuit block LB. Thus, the signal flow is in the direction D2. Therefore, in FIG. 5, the logic circuit HL is arranged on the D2 direction side of the physical layer circuit PHY and the driver logic circuit block LB is arranged on the D2 direction side of the HL in accordance with the signal flow. By doing so, a short path is formed between the input and the output, the signal delay can be optimized, and efficient signal transmission becomes possible.

  If the arrangement is as shown in FIG. 5, the width WH of the HB in the D2 direction can be reduced by increasing the length in the D1 direction of the high-speed I / F circuit block HB. When the width WH of the HB is reduced, the width W of the integrated circuit device 10 in the D2 direction can be reduced, and the chip can be slimmed. This can facilitate mounting.

  FIG. 6 shows a more detailed layout example of the high-speed I / F circuit block HB. In FIG. 6, when the length of the physical layer circuit PHY in the D1 direction is L1, and the length of the logic circuit HL in the D1 direction is L2, the relationship of L2> L1 is established. That is, the length in the long side direction is longer in the logic circuit HL than in the physical layer circuit PHY. In FIG. 6, the protection circuit block PTB1 is arranged in the first area RG1 which is an empty area on the D3 direction side of the physical layer circuit PHY, and the protection circuit is provided in the second area RG2 which is an empty area on the D1 direction side of PHY. Block PTB2 is arranged. Further, capacitor regions CPR1 and CPR2 are arranged in regions RG1 and RG2. Capacitors for stabilizing the power supply of the high-speed I / F circuit block HB are formed in the capacitor regions CPR1 and CPR2. That is, a capacitor is formed between the high potential side power supply (VDD) and the low potential side power supply (VSS) of the high-speed I / F circuit block HB. This capacitor can be formed by utilizing the gate capacitance of the basic cell of the gate array (G / A).

  A number of signals such as data signals and control signals are wired between the logic circuit HL and the driver logic circuit LB. Therefore, it is desirable that the signal wiring area (interface area) between HL and LB is as large as possible.

  In this regard, in FIG. 6, the driver logic circuit block LB is disposed on the D2 direction side of the logic circuit HL, and the length L2 of the HL in the D1 direction is increased. Accordingly, the length of the signal wiring region between the logic circuit HL and the driver logic circuit block LB in the D1 direction can be increased. That is, the length of the signal wiring region in the D1 direction can be set to L2. Therefore, for example, when the wiring pitch of the signal lines is PTH, (L2 / PTH) signal lines can be wired between HL and LB. In addition, the wiring between HL and LB can be connected by a short path, and the width of the signal wiring region in the D2 direction can be reduced. As a result, the width W of the integrated circuit device 10 in the D2 direction can be reduced, the chip can be slimmed, and the mounting can be facilitated.

  Further, when the length L2 of the logic circuit HL is made longer than the length L1 of the physical layer circuit PHY, empty areas RG1 and RG2 are formed on both sides of the PHY.

  In this regard, in FIG. 6, protection circuit blocks PTB1 and PTB2 and capacitor areas CPR1 and CPR2 are arranged in the empty areas RG1 and RG2. Therefore, the protection circuit blocks PTB1, PTB2, etc. can be arranged by effectively using the empty areas RG1, RG2 formed by setting L2> L1. That is, it is possible to simultaneously reduce the widths W and WH in the D2 direction by efficient wiring between HL and LB, and improve the electrostatic withstand voltage and noise resistance by disposing PTB1 and PTB2 on both sides of the PHY. Further, since the capacitor regions CPR1 and CPR2 are formed in the empty regions RG1 and RG2, the power source can be stabilized and noise resistance and the like can be further improved.

  FIG. 7 shows a detailed layout example of the integrated circuit device 10. The integrated circuit device 10 includes a high-speed I / F circuit block HB and a driver logic circuit block LB. Further, it includes a gradation voltage generation circuit block GB for generating gradation voltages, and data driver blocks DB1 and DB2 for driving data lines of the display panel based on the generated gradation voltages. In addition, memory blocks MB1 and MB2 that store image data as gradation data, scan driver blocks SB1 and SB2 that drive scan lines of the display panel, and power supply circuit blocks PB1 and PB2 that generate power are included. Furthermore, I / O areas IO1 and IO2 and a pad area PDS (pad area for data lines and scanning lines) are included.

  As shown in FIG. 7, the high-speed I / F circuit block HB and the driver logic circuit block LB are arranged adjacent to each other. Specifically, when the direction from the side SD2 to the side SD4 is the D2 direction, HB and LB are adjacently arranged along the D2 direction. The LB and the gradation voltage generation circuit block GB are also arranged adjacent to each other. Specifically, LB and GB are also arranged adjacently along the D2 direction.

  In FIG. 7, the gradation voltage generation circuit block GB and the data driver blocks DB1 and DB2 are arranged adjacent to each other. Specifically, when the direction from the side SD1 to the side SD3 is the D1 direction, GB and DB1, DB2 are arranged adjacent to each other along the D1 direction.

  For example, the gradation voltage generation circuit block GB includes an adjustment register (not shown). In this adjustment register, adjustment data for performing gradation voltage amplitude adjustment, gradation characteristic inclination adjustment, gradation characteristic fine adjustment, and the like is set by the driver logic circuit block LB. By setting such adjustment data, it is possible to obtain optimum gradation characteristics (γ characteristics) according to the type of display panel, and to improve display quality.

  However, the number of bits of adjustment data for performing such adjustment is very large. For this reason, the number of adjustment data signal lines from the driver logic circuit block LB to the gradation voltage generation circuit block GB is also large. Therefore, if LB and GB are not arranged adjacent to each other, the chip area may increase due to the wiring area for the adjustment data signal line.

  In this regard, in FIG. 7, the driver logic circuit block LB and the gradation voltage generation circuit block GB are arranged adjacent to each other along the direction D2. Therefore, since the signal line of the adjustment data from the LB can be connected to the GB by a short path, an increase in the chip area due to the wiring region can be prevented.

  The data driver blocks DB1 and DB2 include a D / A conversion circuit (not shown). The D / A conversion circuit receives a plurality of gradation voltages from the gradation voltage generation circuit block GB. Then, by selecting a voltage corresponding to the gradation data from these gradation voltages, D / A conversion of the gradation data is performed. Therefore, the number of gradation voltage signal lines from the gradation voltage generation circuit block GB to the data driver blocks DB1 and DB2 is also large. Therefore, unless GB and DB1 and DB2 are arranged adjacent to each other, there is a possibility that the chip area increases due to the wiring area for the signal line of the gradation voltage.

  In this regard, in FIG. 7, the gradation voltage generation circuit block GB and the data driver blocks DB1 and DB2 are arranged adjacent to each other along the direction D1. Therefore, since the grayscale voltage signal line from GB can be connected to DB1 and DB2 by a short path, an increase in chip area due to the wiring region can be prevented.

5. Arrangement of Protection Circuit FIG. 8 shows a first layout example of the protection circuit included in the protection circuit blocks PTB1 and PTB2. As shown in FIG. 8, the high-speed I / F circuit block HB includes a physical layer circuit PHY, a logic circuit HL, and a power supply line PL of a shared power supply VSSA (ESD dummy power supply). The power supply line PL is wired along the direction D1, for example, in the high-speed I / F circuit block HB.

  The protection circuit block PTB1 includes a protection circuit PT1 provided between the power supply VSSM of the physical layer circuit PHY and the shared power supply VSSA. Further, a protection circuit PT2 provided between the power supply VSSG of the logic circuit HL and the shared power supply VSSA, or a protection circuit PT3 provided between the power supply VSS of the other circuit block (driver logic circuit block or the like) and the shared power supply VSSA. including.

  The protection circuit block PTB2 includes a protection circuit PT4 provided between the power supply VSSM and the shared power supply VSSA. Further, a protection circuit PT5 provided between the power supply VSSG and the shared power supply VSSA and a protection circuit PT6 provided between the power supply VSS and the shared power supply VSSA are included.

  FIG. 9 shows a second layout example of the protection circuit included in the protection circuit blocks PTB1 and PTB2. In FIG. 9, unlike FIG. 8, the high-speed I / F circuit block HB does not include the power supply line of the shared power supply VSSA. The protection circuit block PTB1 includes a protection circuit PT1 provided between VSSM and VSS and a protection circuit PT2 provided between VSSG and VSS. The protection circuit block PTB2 includes a protection circuit PT4 provided between VSSM and VSS and a protection circuit PT5 provided between VSSG and VSS.

  8 and 9, when the physical layer circuit PHY includes a high-speed logic circuit such as a serial / parallel conversion circuit, a power supply for the high-speed logic circuit may be provided. In this case, each of the protection circuit blocks PTB1 and PTB2 may further include a protection circuit provided between the power supply for the high-speed logic circuit and VSSA or VSS.

  8 and 9, the protection circuit PT2 is disposed on the D3 direction side of the protection circuit PT1, and the protection circuit PT5 is disposed on the D1 direction side of the protection circuit PT4. In FIG. 8, the protection circuit PT3 is further disposed on the D3 direction side of the protection circuit PT2, and the protection circuit PT6 is disposed on the D1 direction side of the protection circuit PT5.

  8 and 9, the second power supply line PL2 connecting the protection circuit PT2 and the logic circuit HL is wired on the D3 direction side of the first power supply line PL1 connecting the protection circuit PT1 and the physical layer circuit PHY. The Similarly, a fifth power supply line PL5 connecting the protection circuit PT5 and the logic circuit HL is wired on the D1 direction side of the fourth power supply line PL4 connecting the protection circuit PT4 and the physical layer circuit PHY.

  Specifically, the power supply lines PL1 and PL4 are wired along the D2 direction from the protection circuits PT1 and PT4 to be connected to the physical layer circuit PHY, and then bent and wired in the D1 direction or the D3 direction. These PL1 and PL4 are power supply lines for supplying the power supply VSSM from the pads (electrodes) P1 and P4 to the physical layer circuit PHY.

  Further, the power supply lines PL2 and PL5 are wired along the direction D2 from the protection circuits PT2 and PT5 in order to connect to the logic circuit HL. These PL2 and PL5 are power supply lines for supplying the power supply VSSG from the pads P2 and P5 to the logic circuit HL.

  8 and 9, the pad P1 to which the power supply line PL1 is connected is disposed on the D4 direction side of the protection circuit PT1, and the pad P2 to which the power supply line PL2 is connected is disposed on the D4 direction side of the protection circuit PT2. Is done. That is, the pad P2 is disposed on the D3 direction side of the pad P1. Similarly, the pad P4 to which the power supply line PL4 is connected is disposed on the D4 direction side of the protection circuit PT4, and the pad P5 to which the power supply line PL5 is connected is disposed on the D4 direction side of the protection circuit PT5. That is, the pad P5 is disposed on the D1 direction side of the pad P4.

  8 and 9, reception pads DP and DM (or transmission pads may be provided) of the physical layer circuit PHY are provided. These DP and DM are pads for the differential data signals (DATA +/−, DTO +/−) described with reference to FIGS. 2 (A) to 3 (B). 8 and 9, these pads DP and DM are arranged between the pad P1 and the pad P4.

  8 and 9, static electricity from the power supply VSS of other external circuit blocks can be efficiently discharged by the protection circuits disposed on both sides of the physical layer circuit PHY. Therefore, it is possible to effectively prevent the breakdown of the transistors such as the physical layer circuit PHY.

  8 and 9, the power supply line PL of the power supply VSSA or VSS is wired along the D1 direction, and the power supply lines PL1, PL2, PL4, and PL5 of the power supplies VSSM and VSSG are wired along the D2 direction. Therefore, the protection circuits PT1, PT2, PT4, and PT5 can be disposed near the intersections between the power lines PL1, PL2, PL4, and PL5 and the power lines PL, thereby realizing an efficient layout.

  8 and 9, the power supply lines PL1 and PL2 can be wired without crossing, and the power supply lines PL4 and PL5 can also be wired without crossing. Accordingly, the power lines PL1, PL2, PL4, and PL5 having sufficient thicknesses can be wired using the empty areas RG1 and RG2, and the power supply VSSM and VSSG supplied to the physical layer circuit PHY and the logic circuit HL can be connected. Stabilize. Furthermore, if the capacitor regions CPR1 and CPR2 are formed in the regions RG1 and RG2 and one end of the capacitor is connected to the power supply line, the power supply can be further stabilized.

6). Triple well structure In this embodiment, as described below, the triple well structure is effectively used to reduce the adverse effects of noise.

  That is, as shown in FIG. 10A, the N-type transistor (first conductivity type transistor in a broad sense) NTR1 included in the high-speed I / F circuit block HB is a P-type well (second conductivity type well in a broad sense) PWLH. Formed. The P-type transistor (second conductivity type transistor in a broad sense) PTR1 included in the high-speed I / F circuit block HB is formed on the P-type substrate (second conductivity type substrate in a broad sense) PSUB so as to surround the P-type well PWLH. N-type well (first conductivity type well in a broad sense) NWLH is formed.

  On the other hand, the N-type transistor NTR2 and the P-type transistor PTR2 included in the driver logic circuit block LB (driver circuit) are not formed in the N-type well NWLH for the high-speed I / F circuit block HB, but are regions other than the NWLH region. Formed. Specifically, the P-type transistor PTR2 is formed in an N-type well NWLD separated from the HB NWLH, and the N-type transistor NTR2 is formed in a P-type substrate PSUB. In this way, the transistors NTR1 and PTR1 constituting the high-speed I / F circuit block HB and the transistors NTR2 and PTR2 constituting the driver logic circuit block LB can be separated by the N-type well NWLH having a triple well structure. Thereby, noise transmission between HB and LB can be prevented using the N-type well NWLH as a barrier. Therefore, HB (PHY) is less susceptible to the adverse effects of noise generated by LB, and the transmission quality of serial transfer can be maintained. In addition, LB or the like is less susceptible to the adverse effects of noise generated by HB, and malfunctions can be prevented. Note that the transistors NTR2 and PTR2 of the LB may be realized with a triple well structure.

  FIG. 10B shows a detailed example of the triple well structure. The N-type wells NWLA1, NWLB1, NWLB2, and NWLB3 in FIG. 10B correspond to the N-type well NWLH in FIG. The P-type well PWLB1 in FIG. 10B corresponds to the P-type well PWLH in FIG. Further, the N-type well NWLB4 in FIG. 10B corresponds to the N-type well NWLD in FIG.

  In FIG. 10B, NNLA1 is a deep well, and NLLB1, NLLB2, NLLB3, and NLLB4 are shallow wells. NWLB2 and NWLB3 are formed in a ring shape. As a result, an N-type well can be formed so as to surround the P-type well PWLB1. In the P-type wells PWLB2 and PWLB3, a P + region (second conductivity type diffusion region in a broad sense) electrically connected to the VSS power supply line is formed. By providing such P-type wells PWLB2, PWLB3 and P + regions, the potential of the P-type substrate PSUB can be stabilized and noise resistance can be improved.

  The P + region (second conductivity type diffusion region) for stabilizing the substrate potential can be formed by, for example, the method described with reference to FIGS.

  In FIG. 11A, a P-type substrate is formed in a ring shape so that a substrate potential stabilizing P + region electrically connected to the power source VSS of the driver logic circuit block LB surrounds the high-speed I / F circuit block HB. It is formed in PSUB. That is, the guard ring in the P + region electrically connected to the VSS power supply line by the contact is formed so as to surround the N-type well NWLH in which the HB is formed. By doing so, the potential of the P-type substrate PSUB at the periphery of the N-type well NWLH is stabilized, so that it is possible to effectively prevent noise generated in the HB from being transmitted to the LB or the like.

  In FIG. 11B, the physical layer circuit PHY included in the HB is formed in an N-type well NWLH1 having a triple well structure, and the logic circuit HL is formed in an N-type well NWLH2 having a triple well structure formed separately from the NWLH1. Formed. Specifically, the N-type transistor constituting the PHY is formed in the P-type well PWLH1. The P-type transistor constituting the PHY is formed in the N-type well NWLH1 formed in the PSUB so as to surround the PWLH1.

  On the other hand, the N-type transistor constituting the logic circuit HL is formed in the P-type well PWLH2. The P-type transistor constituting the HL is formed in the N-type well NWLH2 formed in the PSUB so as to surround the PWLH2.

  As shown in FIG. 11B, the physical layer circuit PHY and the logic circuit HL are formed in another well having a triple well structure. Therefore, it is difficult for PHY to be adversely affected by noise generated in HL, and the transmission quality of serial transfer can be maintained. In addition, the adverse effect of noise generated in the PHY is not easily affected by HL, and the occurrence of malfunctions can be prevented. Further, the N-type well NWLH2 in which the HL is formed serves as a barrier, and noise transmission between the physical layer circuit PHY and the driver logic circuit block LB can be reduced.

  In FIG. 11B, the VSS power line is wired in the high-speed I / F circuit block HB. In other words, not only the peripheral edge of the HB but also the VSS power line is wired inside the HB as indicated by A1 in FIG. A P + region connected to the VSS thus wired is formed in the P-type substrate PSUB between the N-type wells NWLH1 and NWLH2.

  In this way, the potential of the P-type substrate PSUB interposed between the N-type wells NWLH1 and NWLH2 is also stabilized by the P + region formed there. Accordingly, noise generated in HL is difficult to be transmitted to PHY, and noise generated in PHY is also difficult to be transmitted to HL. In addition, if the VSS power line is wired in this way, the protection circuit between the HB power supply VSSM, VSSG, etc. and VSS can be laid out efficiently, improving the layout efficiency and the reliability. Can be compatible.

  Note that the method of forming the N-type well and the P + region in the HB is not limited to FIGS. 11A and 11B. For example, the N-type well in which the PHY analog circuit is formed and the N-type well in which the PHY high-speed logic circuit is formed may be separated. In this way, noise tolerance can be further improved.

7). Bidirectional Diode As shown in FIG. 12, the protection circuits PT1 to PT6 can be constituted by bidirectional diodes (rectifier elements) or the like. FIG. 12 is a circuit example in the case where the power supply line of the shared power supply VSSA is provided as shown in FIG.

  For example, the protection circuits PT1 and PT4 include bidirectional diodes configured by the diodes DI1 and DI2, respectively. Specifically, it includes a first diode DI1 provided between the VSSM power supply node (first power supply node) and the VSSA power supply node (intermediate node) and having a forward direction from VSSM to VSSA. . A second diode DI2 is provided between the power supply node of VSSM and the power supply node of VSSA, and has a forward direction from VSSA to VSSM. Furthermore, a first parasitic diode DP1 provided between the VSS power supply node (second power supply node) and the VSSA power supply node and having a forward direction from VSS to VSSA is included. The parasitic diode DP1 is formed on a junction surface between a P-type substrate (second conductivity type substrate) constituting a triple well structure and an N-type well (first first conductivity type well) thereabove. These P-type substrate and N-type well are PSUB and NWLH constituting the triple well structure of FIG.

  The protection circuits PT3 and PT6 are each provided between VSS and VSSA, provided between the third diode DI3 having a forward direction from VSS to VSSA, and between VSS and VSSA, and from VSSA to VSS. Includes a fourth diode DI4 having a forward direction as the first direction. Furthermore, a second parasitic diode DP2 provided between VSS and VSSA and having a forward direction from VSS to VSSA is included. The parasitic diode DP2 is formed on a junction surface between a P-type substrate (second conductivity type substrate) constituting a triple well structure and an N-type well (second first conductivity type well) thereon.

  The protection circuits PT2 and PT5 are each provided between VSSG and VSSA, and include a fifth diode DI5 whose forward direction is from VSSG to VSSA. Also included is a sixth diode DI6 provided between VSSG and VSSA and having a forward direction from VSSA to VSSG. Further, a third parasitic diode DP3 provided between VSS and VSSA and having a forward direction from VSS to VSSA is included. The parasitic diode DP3 is formed on a junction surface between a P-type substrate (second conductivity type substrate) constituting a triple well structure and an N-type well (third first conductivity type well) thereabove.

  If a protection circuit is formed by such a bidirectional diode, the protection circuit can have an electrostatic protection function and a noise removal function. For example, even when a positive or negative electrostatic voltage is applied between the power supplies VSSM and VSS, the bidirectional diodes of the protection circuits PT1 and PT3 (PT4 and PT6) serve as a discharge path to discharge static electricity. The electrostatic breakdown of the transistor is prevented. Further, when noise from the display driver is applied to the power supply VSS, the noise is removed by the bidirectional diodes of the protection circuits PT1 and PT3 (PT4 and PT6) so that the noise is not transmitted to the power supply VSSM. For example, when the forward voltage of the diode is 0.6V, noise of 1.2V or less is not transmitted to VSSM.

  As shown in FIG. 12, thyristors SCR1, SCR2, and SCR3 are provided between VDDM and VSSM, between VDD and VSS, and between VDDG and VSSG, respectively. Parasitic diodes DP4 and DP7 are formed between VDDM and VSSM and between VDDG and VSSG, respectively. Further, parasitic diodes DP5, DP6 and DP8 are formed between VDDM, VDD, VDDG and VSS.

  FIG. 13 is a circuit example in the case where the power supply line of the shared power supply VSSA as shown in FIG. 9 is not provided. In FIG. 13, the protection circuits PT3 and PT6 of FIG. 12 are not provided. The protection circuits PT1 and PT4 are provided between VSSM and VSS, and the protection circuits PT2 and PT5 are provided between VSSG and VSS.

  14A and 14B are cross-sectional views schematically showing a vertical structure of a diode constituting the protection circuit. In FIG. 14A, an N-type well NWLH1 is formed on a P-type substrate PSUB (second conductivity type substrate) so as to surround the P-type well PWLH1. The diode DI1 is formed at the junction surface between the P + region (first second conductivity type diffusion region) and the N type well NWLH1 (first first conductivity type well) therebelow. The diode DI2 is formed at the junction surface between the N + region (first first conductivity type diffusion region) and the P type well PWLH1 (first second conductivity type well) therebelow. The parasitic diode DP1 is formed on the junction surface between the P-type substrate PSUB and the N-type well NWLH1 thereon.

  In FIG. 14B, an N-type well NWLH2 is formed on a P-type substrate PSUB so as to surround the P-type well PWLH2. The diode DI3 is formed at the junction surface between the P + region (second second conductivity type diffusion region) and the N type well NWLH2 (second first conductivity type well) therebelow. The diode DI4 is formed at the junction surface between the N + region (second first conductivity type diffusion region) and the P type well PWLH2 (second second conductivity type well) therebelow. As described above, the diode DI3 is formed in the N-type well NWLH2 formed separately from the N-type well NWLH1 in which the diode DI1 is formed. The diode DI4 is formed in a P-type well PWLH2 formed separately from the P-type well PWLH1 in which the diode DI2 is formed. The parasitic diode DP2 is formed on the junction surface between the P-type substrate PSUB and the N-type well NWLH2 thereon.

  The diodes DI5 and DI6 also have the same structure as that shown in FIGS. In this case, the diode DI5 is formed in an N-type well (third first conductivity type well) formed separately from the N-type well NWLH1 of the diode DI1 and the N-type well NWLH2 of the diode DI3. The diode DI6 is formed in a P-type well (third second conductivity type well) formed separately from the P-type well PWLH1 of the diode DI2 and the P-type well PWLH2 of the diode DI4.

  FIG. 15 shows a detailed example of a triple well structure in which a diode is formed. PWLB1 in FIG. 15 corresponds to PWLH1 in FIG. 14A, and NWLB1 in FIG. 15 corresponds to NWLH1 in FIG.

  As shown in FIGS. 14A and 14B, parasitic diodes DP1 and DP2 are parasitic on the A terminal of the protection circuit (bidirectional diode). In FIG. 12, the A terminals of the protection circuit in which such a parasitic diode is formed are connected to each other. Specifically, the A terminal of the protection circuit PT1 (PT4) and the A terminal of the protection circuit PT3 (PT6) are connected via a VSSA power line. The A terminal of the protection circuit PT2 (PT5) and the A terminal of the protection circuit PT3 (PT6) are also connected via a VSSA power line.

  With this connection, the parasitic diodes DP1, DP2, and DP3 are parasitic only on the power supply line of the VSSA that is the A terminal. Therefore, the number of diode stages between VSSM and VSSA, the number of diode stages between VSS and VSSA, and the number of diode stages between VSSG and VSSA are all one, and the parasitic diode becomes a noise propagation path. Can be prevented.

  That is, in FIG. 12, when the B terminal of the protection circuit PT1 is connected to VSSA, the parasitic diode DP1 is formed between VSSM and VSS. Therefore, assuming that the forward voltage of DP1 is 0.6V, noise larger than 0.6V is not removed, but propagates from VSS to VSSM.

  On the other hand, in FIG. 12, since VSSA is connected to the A terminal of the protection circuit PT1, the parasitic diode DP1 is formed between VSS and VSSA. Accordingly, not only the number of diode stages in the path of the protection circuits PT3 and PT1, but also the number of diode stages in the path of the parasitic diode DP1 and the protection circuit PT1 is two. Therefore, when the forward voltage of the diode is 0.6V, it is possible to reliably prevent a noise of 1.2V or less from propagating from VSS to VDDM.

8). Elongated Integrated Circuit Device FIG. 16 shows a modification of the layout of the integrated circuit device 10. The integrated circuit device 10 includes first to Nth circuit blocks CB1 to CBN (N is an integer of 2 or more) arranged along the direction D1. The integrated circuit device 10 also includes an output-side I / F region 12 (first interface region in a broad sense) provided along the side SD4 on the D2 direction side of the first to Nth circuit blocks CB1 to CBN. Further, it includes an input-side I / F area 14 (second interface area in a broad sense) provided along the side SD2 on the D4 direction side of the first to Nth circuit blocks CB1 to CBN. More specifically, the output-side I / F region 12 (first I / O region) is arranged on the D2 direction side of the circuit blocks CB1 to CBN without using, for example, other circuit blocks. The input-side I / F area 14 (second I / O area) is arranged on the D4 direction side of the circuit blocks CB1 to CBN, for example, without passing through other circuit blocks.

  The output side (display panel side) I / F area 12 is an area serving as an interface with the display panel, and includes various elements such as a pad, an output transistor connected to the pad, and a protection element. Specifically, it includes an output transistor for outputting a data signal to the data line and a scanning signal to the scanning line. In the case where the display panel is a touch panel, an input transistor may be included.

  The input side (host side) I / F area 14 is an area serving as an interface with the host, and includes various elements such as pads, input (input / output) transistors connected to the pads, output transistors, and protection elements. An element can be included. Specifically, an input transistor for inputting a signal (digital signal) from the host, an output transistor for outputting a signal to the host, and the like are included.

  Note that an output-side or input-side I / F area along the short sides SD1 and SD3 may be provided. Further, bumps or the like serving as external connection terminals may be provided in the I / F (interface) regions 12 and 14, or may be provided in other regions (first to Nth circuit blocks CB1 to CBN). In the case where it is provided in a region other than the I / F regions 12 and 14, it is realized by using a small bump technology (such as a bump technology using a resin as a core) other than the gold bump.

  The first to Nth circuit blocks CB1 to CBN can include at least two (or three) different circuit blocks (circuit blocks having different functions). Taking the case where the integrated circuit device 10 is a display driver as an example, the circuit blocks CB1 to CBN include at least two blocks of a data driver, a memory, a scan driver, a logic circuit, a gradation voltage generation circuit, and a power supply circuit. be able to.

  17A and 17B show detailed examples of the planar layout of the integrated circuit device 10. 17A and 17B, the first to Nth circuit blocks CB1 to CBN are first to fourth memory blocks MB1 to MB4 (first to Ith memory blocks in a broad sense. I is 2). Including the above integer). The first to fourth data driver blocks DB1 to DB4 (first in a broad sense, the first to fourth memory blocks MB1 to MB4) are arranged adjacent to each other along the direction D1. To I-th data driver block). Specifically, the memory block MB1 and the data driver block DB1 are arranged adjacently along the D1 direction, and the memory block MB2 and the data driver block DB2 are arranged adjacently along the D1 direction. The image data (display data) used by the data driver block DB1 to drive the data lines is stored in the adjacent memory block MB1, and the image data used by the data driver block DB2 to drive the data lines is adjacent. Memory block MB2 stores it.

  The layout arrangement of the integrated circuit device 10 of this embodiment is not limited to FIGS. For example, the number of memory blocks or data driver blocks may be 2, 3 or 5 or more, or the memory block or data driver block may be configured not to be divided into blocks. Further, a modification can be made so that the memory block and the data driver block are not adjacent to each other. In addition, a configuration in which a memory block, a scan driver block, a power supply circuit block, a gradation voltage generation circuit block, or the like is not provided may be employed. Further, a circuit block having a very narrow width in the D2 direction (elongated circuit block of WB or less) may be provided between the circuit blocks CB1 to CBN and the output-side I / F region 12 or the input-side I / F region 14. The circuit blocks CB1 to CBN may include circuit blocks in which different circuit blocks are arranged in multiple stages in the D2 direction. For example, the scan driver circuit and the power supply circuit may be configured as one circuit block.

  FIG. 18A shows an example of a cross-sectional view of the integrated circuit device 10 along the direction D2. Here, W1, WB, and W2 are the widths in the D2 direction of the output side I / F region 12, the circuit blocks CB1 to CBN, and the input side I / F region 14, respectively. The widths W1, WB, and W2 are the widths (maximum widths) of the transistor formation regions (bulk region and active region) in the output side I / F region 12, circuit blocks CB1 to CBN, and input side I / F region 14, respectively. Yes, it does not include the bump formation area. W is the width of the integrated circuit device 10 in the direction D2.

  In the present embodiment, as shown in FIG. 18A, in the direction D2, no other circuit block is interposed between the circuit blocks CB1 to CBN and the output side and input side I / F regions 12 and 14. . Therefore, W1 + WB + W2 ≦ W <W1 + 2 × WB + W2. Alternatively, since W1 + W2 <WB holds, W <2 × WB can be set.

  On the other hand, in the arrangement method of FIG. 18B, two or more circuit blocks are arranged along the direction D2. Specifically, the data driver block and the memory block are arranged along the direction D2.

  For example, in FIG. 18B, image data from the host side is written into the memory block. The data driver block converts the digital image data written in the memory block into an analog data voltage, and drives the data lines of the display panel. Accordingly, the signal flow of the image data is in the direction D2. For this reason, in FIG. 18B, the memory block and the data driver block are arranged along the direction D2 in accordance with the flow of this signal.

  However, the arrangement method of FIG. 18B has the following problems.

  First, in an integrated circuit device such as a display driver, a reduction in chip size is required for cost reduction. However, if a fine process is employed and the integrated circuit device is simply shrunk to reduce the chip size, not only the short side direction but also the long side direction is reduced, and mounting becomes difficult due to the narrow pitch.

  Secondly, in the display driver, the configuration of the memory and data driver varies depending on the type of display panel (amorphous TFT, low-temperature polysilicon TFT), the number of pixels (QCIF, QVGA, VGA), product specifications, and the like. Therefore, in the arrangement method of FIG. 18B, even if the pad pitch, the memory cell pitch, and the data driver cell pitch match in a certain product, these pitches do not match if the configuration of the memory or data driver changes. . If the pitches do not match, it becomes necessary to form a useless wiring region for absorbing the pitch mismatch between the circuit blocks. As a result, the width of the integrated circuit device in the direction D2 is increased, the chip area is increased, and the cost is increased. On the other hand, in order to avoid such a situation, if the layout of the memory or data driver is changed so that the pad pitch and the cell pitch are aligned, the development period becomes longer, resulting in an increase in cost.

  On the other hand, in the arrangement methods of FIGS. 16, 17A, and 17B, a plurality of circuit blocks CB1 to CBN are arranged along the direction D1. In FIG. 18A, a transistor (circuit element) can be disposed under the pad (bump) (active surface bump). In addition, signal lines between circuit blocks, between circuit blocks and I / F regions, and the like can be formed by global wiring formed in a layer above the local wiring (lower layer than the pad) that is a wiring in the circuit block. Therefore, the width W in the D2 direction can be narrowed while maintaining the length of the integrated circuit device 10 in the D1 direction, and a slim elongated chip can be realized.

  In addition, the circuit blocks CB1 to CBN are arranged along the direction D1 in the arrangement methods of FIGS. 16, 17A, and 17B, so that it is possible to easily cope with a change in product specifications. In other words, since it is possible to design products with various specifications using a common platform, the design efficiency can be improved. For example, in FIGS. 17A and 17B, even when the number of pixels and the number of gradations of the display panel increase or decrease, the number of memory blocks and data driver blocks, the number of times image data is read out in one horizontal scanning period, etc. Just increase or decrease the number. FIGS. 17A and 17B are examples for an amorphous TFT panel with a built-in memory. When developing a product for a low-temperature polysilicon TFT panel with a built-in memory, scanning is performed from among the circuit blocks CB1 to CBN. Just remove the driver block. When developing a product without a memory, the memory block can be removed. Even if the circuit block is removed in accordance with the specifications as described above, the influence of the circuit block on other circuit blocks can be minimized, so that the design efficiency can be improved.

  In the arrangement methods shown in FIGS. 16, 17A, and 17B, the width (height) of each circuit block CB1 to CBN in the D2 direction is unified to, for example, the width (height) of the data driver block or the memory block. it can. When the number of transistors in each circuit block increases / decreases, the design can be made more efficient because it can be adjusted by increasing / decreasing the length of each circuit block in the D1 direction. For example, in FIGS. 17A and 17B, even when the configuration of the gradation voltage generation circuit block or the power supply circuit block is changed and the number of transistors increases or decreases, the direction of the gradation voltage generation circuit block or the power supply circuit block in the direction D1 This can be dealt with by increasing or decreasing the length.

  Even when the arrangement methods of FIGS. 16, 17A and 17B are adopted, as shown in FIG. 19A, the protection circuit blocks PTB1 and PTB2 are provided on both sides of the high-speed I / F circuit block HB. Be placed. As a result, it is possible to prevent electrostatic breakdown and remove noise from the transistors of the high-speed I / F circuit block HB. In addition, the length in the D1 direction of the wiring region between the high-speed I / F circuit block HB and the logic circuit block LB can be increased, and the wiring efficiency can be improved. Further, since the width in the D2 direction of the high-speed I / F circuit block HB can be reduced, the width W in the D2 direction of the integrated circuit device can also be reduced, and a slim and slender chip can be realized.

  Further, the high-speed I / F circuit block HB may be arranged as shown in FIG. In FIG. 19B, the logic circuit block LB is arranged adjacent to the high-speed I / F circuit block HB in the direction D1 (or D3). Even in the case of FIG. 19B, the protection circuit blocks PTB1 and PTB2 are arranged on both sides of the high-speed I / F circuit block HB. Accordingly, it is possible to prevent electrostatic breakdown and eliminate noise, and to increase the wiring efficiency between the HB and LB by increasing the length of the wiring region.

9. Electronic Device FIGS. 20A and 20B show examples of electronic devices (electro-optical devices) including the integrated circuit device 10 of the present embodiment. Note that the electronic apparatus may include components (for example, a camera, an operation unit, a power supply, or the like) other than those illustrated in FIGS. The electronic device according to the present embodiment is not limited to a mobile phone, and may be a digital camera, a PDA, an electronic notebook, an electronic dictionary, a projector, a rear projection television, a portable information terminal, or the like.

  20A and 20B, the host device 410 is, for example, an MPU, a baseband engine, or the like. The host device 410 controls the integrated circuit device 10 that is a display driver. Alternatively, processing as an application engine or baseband engine, or processing as a graphic engine such as compression, decompression, or sizing can be performed. The image processing controller 420 in FIG. 20B performs processing as a graphic engine such as compression, decompression, and sizing on behalf of the host device 410.

  In the case of FIG. 20A, the integrated circuit device 10 having a built-in memory can be used. That is, in this case, the integrated circuit device 10 once writes the image data from the host device 410 into the built-in memory, reads the written image data from the built-in memory, and drives the display panel. On the other hand, in the case of FIG. 20B, an integrated circuit device 10 without a memory can be used. That is, in this case, the image data from the host device 410 is written into the built-in memory of the image processing controller 420. The integrated circuit device 10 drives the display panel 400 under the control of the image processing controller 420.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, different terms having a broader meaning or the same meaning (first conductivity type well, second conductivity type well, first conductivity type diffusion region, second conductivity type diffusion region, first conductivity type transistor) , Second conductivity type transistor, second conductivity type substrate, etc.) (N-type well, P-type well, N + region, P + region, N-type transistor, P-type transistor, P-type substrate, etc.) The different terms can be used anywhere in the book or drawing. Further, the configuration, arrangement, and operation of the integrated circuit device and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

6 is a circuit configuration example of an integrated circuit device. 2A, 2B, and 2C are configuration examples of a high-speed I / F circuit and a physical layer circuit. 3A and 3B show other configuration examples of the physical layer circuit. 6 is a layout example of an integrated circuit device. 4 is a detailed layout example of an integrated circuit device. 3 shows a detailed layout example of a high-speed I / F circuit block. 4 shows a more detailed layout example of an integrated circuit device. 1 is a first layout example of a protection circuit. The 2nd layout example of a protection circuit. 10A and 10B are explanatory diagrams of a method using a triple well. 11A and 11B are explanatory diagrams of a method for forming a P + region. Explanatory drawing of a bidirectional diode. Explanatory drawing of a bidirectional diode. 14A and 14B are schematic cross-sectional views showing a vertical structure of a diode. The detailed sectional view showing the vertical structure of a diode. 6 shows a modified example of the layout of the integrated circuit device. 17A and 17B are detailed examples of the planar layout of the integrated circuit device. 18A and 18B are examples of cross-sectional views of an integrated circuit device. 19A and 19B show examples of arrangement of protection circuit blocks. 20A and 20B are configuration examples of electronic devices.

Explanation of symbols

HB high-speed I / F circuit block, logic circuit block for LB driver,
PHY physical layer circuit, HL logic circuit,
PTB1, PTB2 first and second protection circuit blocks, PT1 to PT6 protection circuit,
P1, P2, P4, P5, DP, DM pad,
PL1, PL2, PL4, PL5 power line, RG1, RG2 first and second regions,
CPR1, CPR2 first and second capacitor regions,
10 integrated circuit device, 12 output side I / F area, 14 input side I / F area,

Claims (16)

A high-speed interface circuit block including a physical layer circuit for transferring data via a serial bus, and at least one other circuit block;
The high-speed interface circuit block includes:
The first comprises a second protection circuit block,
Each of the first and second protection circuit blocks includes at least one protection circuit provided between the power supply of the high-speed interface circuit block and the power supply of the other circuit block .
The first protection circuit block is disposed closer to the first side than the second protection circuit block when the short side of the high-speed interface circuit block is the first side .
The second protection circuit block is located closer to the third side than the first protection circuit block when a side opposite to the first side of the high-speed interface circuit block is a third side. An integrated circuit device which is arranged. In claim 1,
The integrated circuit device, wherein the physical layer circuit is disposed between the first and second protection circuit blocks. In claim 1 or 2,
  The third direction of the physical layer circuit when the direction from the first side to the third side is the first direction and the direction opposite to the first direction is the third direction The integrated circuit device, wherein the first protection circuit block is disposed on a side of the physical layer circuit, and the second protection circuit block is disposed on a side of the physical layer circuit in the first direction. In any one of Claims 1 thru | or 3 ,
The high-speed interface circuit block includes the physical layer circuit and a logic circuit,
The direction from the first side to the third side of the high-speed interface circuit block is defined as a first direction, and the second side, which is the long side of the high-speed interface circuit block, is directed to the fourth side facing the first side. The logic circuit is arranged on the second direction side of the physical layer circuit when the direction toward the second direction is the second direction. In claim 4 ,
As the other circuit block, including a driver logic circuit block that generates a display control signal,
The integrated circuit device, wherein the driver logic circuit block is disposed on the second direction side of the logic circuit. In claim 4 or 5 ,
An integrated circuit, wherein L2> L1, where L1 is a length of the physical layer circuit in the first direction and L2 is a length of the logic circuit in the first direction. apparatus. In claim 6 ,
When the direction opposite to the first direction is a third direction, the first protection circuit block is disposed in a first region on the third direction side of the physical layer circuit, and the physical layer circuit The integrated circuit device is characterized in that the second protection circuit block is arranged in the second region on the first direction side. In claim 7 ,
An integrated circuit device, wherein a capacitor region in which a capacitor provided between a high potential side power source and a low potential side power source of the high-speed interface circuit block is formed in the first and second regions. In any one of Claims 1 thru | or 8 .
The high-speed interface circuit block includes the physical layer circuit, a logic circuit, and a power line of a shared power source,
The first protection circuit block includes:
A first protection circuit provided between a power supply of the physical layer circuit and the shared power supply;
A second protection circuit provided between the power supply of the logic circuit and the shared power supply;
A third protection circuit provided between the power supply of the other circuit block and the shared power supply;
The second protection circuit block includes:
A fourth protection circuit provided between the power supply of the physical layer circuit and the shared power supply;
A fifth protection circuit provided between the power supply of the logic circuit and the shared power supply;
An integrated circuit device comprising a sixth protection circuit provided between a power supply of the other circuit block and the shared power supply. In any one of Claims 1 thru | or 8 .
The high-speed interface circuit block includes the physical layer circuit and a logic circuit,
The first protection circuit block includes:
A first protection circuit provided between the power supply of the physical layer circuit and the power supply of the other circuit block;
A second protection circuit provided between the power supply of the logic circuit and the power supply of the other circuit block;
The second protection circuit block includes:
A fourth protection circuit provided between the power supply of the physical layer circuit and the power supply of the other circuit block;
An integrated circuit device comprising a fifth protection circuit provided between a power supply of the logic circuit and a power supply of the other circuit block. In claim 9 or 10 ,
When the direction from the first side to the third side of the high-speed interface circuit block is the first direction and the direction opposite to the first direction is the third direction,
The second protection circuit is disposed on the third direction side of the first protection circuit;
The integrated circuit device, wherein the fifth protection circuit is arranged on the first direction side of the fourth protection circuit. In claim 11 ,
A second power supply line connecting the second protection circuit and the logic circuit is wired on the third direction side of the first power supply line connecting the first protection circuit and the physical layer circuit,
A fifth power supply line connecting the fifth protection circuit and the logic circuit is wired on the first direction side of the fourth power supply line connecting the fourth protection circuit and the physical layer circuit. An integrated circuit device. In claim 12 ,
When the direction from the second side, which is the long side of the high-speed interface circuit block, to the fourth side facing the second direction is the second direction, and the direction opposite to the second direction is the fourth direction,
A first pad to which the first power line is connected is disposed on the fourth direction side of the first protection circuit;
A second pad to which the second power line is connected is disposed on the third direction side of the first pad;
A fourth pad connected to the fourth power line is disposed on the fourth direction side of the fourth protection circuit;
5. An integrated circuit device according to claim 5, wherein a fifth pad to which the fifth power supply line is connected is disposed on the first direction side of the fourth pad. In claim 13 ,
An integrated circuit device, wherein at least one of a receiving pad or a transmitting pad of the physical layer circuit is disposed between the first pad and the fourth pad. In any one of Claims 1 thru | or 14 .
The integrated circuit device, wherein the protection circuit included in the first and second protection circuit blocks includes a bidirectional diode. An integrated circuit device according to any one of claims 1 to 15 ,
A display panel driven by the integrated circuit device;
An electronic device comprising:

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