JP4305497B2 - Integrated circuit device and electronic device - Google Patents

Description

  The present invention relates to an integrated circuit device and an electronic apparatus.

  In recent years, high-speed serial transfer such as LVDS (Low Voltage Differential Signaling) has attracted attention as an interface for the purpose of reducing EMI noise. In this high-speed serial transfer, the transmitter circuit transmits serialized data as a differential signal, and the receiver circuit differentially amplifies the differential signal to realize data transfer.

  A general mobile phone includes a first device portion provided with buttons for inputting a telephone number and characters, a second device portion provided with an LCD (Liquid Crystal Display) and a camera device, and first and first devices. It is comprised by connection parts, such as a hinge which connects two apparatus parts. Therefore, data transfer between the first circuit board provided in the first device portion and the second circuit board provided in the second device portion is performed by high-speed serial transfer using a small amplitude differential signal. This is advantageous because the number of wires passing through the connection portion can be reduced.

  Incidentally, there is a display driver (LCD driver) as an integrated circuit device for driving a display panel such as a liquid crystal panel. In order to realize high-speed serial transfer between the first and second device parts described above, a high-speed interface circuit that performs data transfer via the serial bus needs to be incorporated in the display driver.

However, since the high-speed interface circuit handles a differential signal having a small amplitude such as a voltage amplitude of 0.1 V to 1.0 V, for example, there is a problem that it is easily affected by noise from other signal lines. In particular, it has been found that when noise of a signal having a large amplitude such as a scanning signal of a scanning line is transmitted to a high-speed interface circuit, a malfunction such as a transfer error may occur.
JP 2001-222249 A

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to provide an integrated circuit device capable of preventing a malfunction or the like when a high-speed interface circuit is incorporated, and an electronic apparatus including the integrated circuit device. It is to provide.

  The present invention provides at least one scan driver block for driving a scan line of a display panel, a high-speed interface circuit block for transferring data via a serial bus using a differential signal, and a scan output of the scan driver block A physical layer circuit for receiving data using the differential signal, wherein the high-speed interface circuit block includes a scanning driver pad arrangement region in which pads for electrically connecting the line and the scanning line are arranged. And a link controller that performs link layer processing, and a scan output line that is an output line of the scan driver block bypasses the physical layer circuit on the link controller from the scan driver block to the scan driver. The present invention relates to an integrated circuit device that is wired to a pad arrangement region.

  According to the present invention, since the high-speed interface circuit block is incorporated in the integrated circuit device, high-speed serial transfer using a differential signal with an external device becomes possible. Also, since the integrated circuit device includes a scan driver block, it is necessary to wire a large number of scan output lines from the scan driver block to the scan driver pad arrangement region. There is a possibility of adversely affecting the block. In this regard, according to the present invention, the scanning output line of the scanning driver block is wired so as to bypass the physical layer circuit. Therefore, it is possible to effectively prevent the change in the voltage level of the scanning output line from being transmitted as signal noise to the physical layer circuit. Therefore, it is possible to provide an integrated circuit device that can prevent malfunctions and the like when a high-speed interface circuit block is incorporated.

  In the present invention, the high-speed interface circuit block and the scan driver block are arranged along a first direction, and the high-speed interface circuit block is obtained when a direction orthogonal to the first direction is a second direction. In addition, the scan driver pad arrangement region may be provided on the second direction side of the scan driver block.

  In such an arrangement relationship, if the scanning output line is wired without taking any signal noise into consideration, the scanning output line is wired on the physical layer circuit. In this regard, according to the present invention, since the scanning output lines are routed on the link controller bypassing the physical layer circuit, wiring of a large number of scanning output lines from the scanning driver block and reduction of adverse effects of signal noise are reduced. Can be compatible.

  In the present invention, the link controller may be arranged on the second direction side of the physical layer circuit.

  In this way, the scanning output line can be wired by effectively utilizing the wiring area on the link controller arranged on the second direction side of the physical layer circuit, so that the layout efficiency can be improved.

  The present invention also includes a logic circuit block that receives the data received by the high-speed interface circuit block and controls the scan driver block, and the high-speed interface circuit block is between the logic circuit block and the scan driver block. May be arranged.

  In this way, it is possible to prevent signal noise from, for example, a signal line wired in the third direction side of the logic circuit block from adversely affecting the high-speed interface circuit block.

  In the present invention, the logic circuit block and the link controller may be integrated and formed by automatic placement / wiring.

  In this way, the logic circuit block and the link controller, which are the main logic parts of the integrated circuit device, can be formed by, for example, one automatic placement / wiring, so that the design efficiency and work efficiency can be improved.

  In the present invention, in the link controller, a shield line may be wired under the scan output line of the scan driver block passing over the link controller.

  In this way, it is possible to prevent noise due to a change in the voltage level of the scanning output line from being transmitted to the circuits and signal lines in the link controller by the coupling capacitance.

  In the present invention, at least one data driver block for driving the data lines of the display panel, a common voltage generating circuit for generating a common voltage applied to the counter electrode of the display panel, and the common voltage generating circuit Including a first and a second common voltage pad for outputting the common voltage generated in step 2 to the outside, a direction orthogonal to the first direction is defined as a second direction, and a direction opposite to the first direction is defined as a second direction. The first common voltage pad is disposed on the third direction side of the data driver block when the third direction is the fourth direction and the direction opposite to the second direction is the fourth direction. Two common voltage pads are arranged on the first direction side of the data driver block, and the first and second differences for inputting the first and second signals constituting the differential signal from the outside. Moving in A pad is disposed on the fourth direction side of the physical layer circuit, and a common voltage line connecting the first and second common voltage pads is connected to the second common voltage pad from the first common voltage pad. Wiring is performed along the first direction with respect to the voltage pad, and wiring is performed along the first direction on the second direction side of the physical layer circuit in the arrangement region of the physical layer circuit. Also good.

  According to the present invention, the first and second common voltage pads are connected by the common voltage line. As a result, it is possible to reduce display quality deterioration due to an imbalance of parasitic resistance values of the common voltage line. The common voltage line is wired along the first direction on the second direction side of the physical layer circuit. Therefore, it is possible to prevent noise from the common voltage line from being superimposed on the differential signal of the physical layer circuit, and it is possible to prevent occurrence of a malfunction in the high-speed interface circuit due to noise.

  In the present invention, the common voltage line may be wired along the first direction on the fourth direction side of the data driver block in the arrangement region of the data driver block.

  In this way, it is possible to prevent the display quality from deteriorating due to fluctuations in the level of the common voltage due to noise from the data signal line.

  In the present invention, the common voltage line may be wired along the first direction on the second direction side of the link controller.

  In this way, signal line noise between the physical layer circuit and the link controller can be prevented from being transmitted to the common voltage line.

  In the present invention, the first shield line formed of a wiring layer different from the common voltage line and supplied with a given power supply potential may be wired so as to overlap the common voltage line. .

  In this way, noise from above or below the common voltage line can be effectively shielded by the first shield line.

  In the present invention, a second shield line formed of the same wiring layer as the common voltage line and supplied with a given power supply potential may be wired on both sides of the common voltage line.

  In this way, noise from both sides of the common voltage line can be effectively shielded by the second shield line.

  In the present invention, first to Nth circuit blocks (N is an integer of 2 or more) are arranged along the first direction, and the first to Nth circuit blocks are arranged to connect the data lines of the display panel. At least one data driver block for driving, a grayscale voltage generation circuit block for generating a plurality of grayscale voltages, and data received by the high-speed interface circuit block, and for adjusting the grayscale voltage A logic circuit block that transfers gradation adjustment data to the gradation voltage generation circuit block, wherein a direction orthogonal to the first direction is a second direction, and a direction opposite to the first direction is a third direction The gradation voltage generation circuit block is arranged on the third direction side of the data driver block, and the fourth direction is a direction opposite to the second direction. High-speed interface circuit block and the logic circuit block may be arranged in the first direction side of the data driver block.

  In this way, since the first to Nth circuit blocks are arranged along the first direction, the width of the integrated circuit device in the second direction can be reduced, and the area can be reduced. In addition, wiring using the empty space on the second direction side of the gradation voltage generation circuit block and the logic circuit block is possible, and wiring efficiency can be improved. Further, since the data driver block can be concentrated and arranged near the center of the integrated circuit device, the output line of the data signal from the data driver block can be efficiently and simply wired.

  In the present invention, a local line formed by a wiring layer lower than the I-th (I is an integer of 3 or more) layer is wired between adjacent circuit blocks among the first to N-th circuit blocks. In addition, between the non-adjacent circuit blocks among the first to Nth circuit blocks, a global line formed by a wiring layer higher than the I-th layer is on a circuit block interposed between non-adjacent circuit blocks. A global line for gradation that is wired along the first direction and supplies the gradation voltage from the gradation voltage generation circuit block to the data driver is arranged on the data driver block in the first direction. It may be wired along.

  In this way, since adjacent circuit blocks are connected by a short path by a local line, an increase in chip area due to the wiring region can be prevented. In addition, since global lines are routed between circuit blocks that are not adjacent to each other, even when the number of local lines is large, grayscale global lines can be wired on these local lines.

  In the present invention, first to Nth circuit blocks (N is an integer of 2 or more) are arranged along the first direction, and the first to Nth circuit blocks are arranged to connect the data lines of the display panel. Receiving at least one data driver block for driving, a power supply circuit block for generating a power supply voltage, and data received by the high-speed interface circuit block, and supplying power adjustment data for adjusting the power supply voltage A logic circuit block transferred to the power supply circuit block, a direction orthogonal to the first direction is a second direction, a direction opposite to the first direction is a third direction, and the second direction is When the opposite direction is the fourth direction, the power supply circuit block is arranged on the third direction side of the data driver block, and the high-speed interface circuit is arranged. Block and the logic circuit block may be arranged in the first direction side of the data driver block.

  In this way, wiring using the empty space on the second direction side of the power circuit block and logic circuit block becomes possible, and wiring efficiency can be improved.

  In the present invention, a local line formed by a wiring layer lower than the I-th (I is an integer of 3 or more) layer is wired between adjacent circuit blocks among the first to N-th circuit blocks. In addition, between the non-adjacent circuit blocks among the first to Nth circuit blocks, a global line formed by a wiring layer higher than the I-th layer is on a circuit block interposed between non-adjacent circuit blocks. A global line for power supply that is wired along the first direction and supplies a power supply voltage from the power supply circuit block may be wired along the first direction on the data driver block.

  In this way, global lines are routed between non-adjacent circuit blocks, so even when the number of local lines is large, power global lines can be wired on these local lines. Can be improved.

  The present invention also relates to an electronic apparatus including any one of the integrated circuit devices described above and a display panel driven by the integrated circuit device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. In recent years, high-speed I / F circuits (high-speed interface circuits) that serially transfer data using differential signals have attracted attention. Since this high-speed I / F circuit handles a differential signal with a small amplitude, it is easily affected by noise, and there is a possibility that a malfunction such as a data transfer error may occur due to the noise. Therefore, it is desirable to minimize the influence of noise on the high-speed I / F circuit. On the other hand, when a scanning driver (gate driver) is provided in an integrated circuit device such as a display driver, the amplitude of the output signal of the scanning driver is, for example, about 10 to 20 V, which is much larger than the amplitude of the differential signal. Therefore, if no measures are taken, the high-speed I / F circuit may malfunction due to noise in the output signal of the scan driver.

  FIG. 1 shows an arrangement configuration example of the integrated circuit device 10 of the present embodiment. As shown in FIG. 1, the integrated circuit device 10 includes at least one scan driver block SB for driving a scan line of a display panel, and a high-speed I / F that performs data transfer via a serial bus using a differential signal. A circuit block HB is included. The high-speed I / F circuit block HB includes a physical layer circuit PHY and a link controller LKC. Further, the integrated circuit device 10 is provided with a scan driver pad arrangement region PR in which pads for electrically connecting the scan output lines, which are output lines of the scan driver block SB, and the scan lines are arranged.

  The scanning driver block SB outputs a scanning signal (gate signal) having an amplitude of about 10 to 20 V, which is a selection signal for the scanning line of the display panel. This scanning signal is input to the pad of the scanning driver pad arrangement region PR via the scanning output line indicated by H1. Then, it is output to the scanning line (gate line) of the external display panel through these pads.

  The physical layer circuit PHY included in the high-speed I / F circuit block HB is a circuit for performing data transfer via a serial bus using a differential signal, and receives data (packets) using the differential signal, for example. . Specifically, the physical layer circuit PHY can include a receiver circuit to which first and second signals constituting a small amplitude differential signal are input. A serial / parallel conversion circuit that converts serial data received via the serial bus into parallel data may be included. Or you may include the transmitter circuit which transmits data using a differential signal, and the parallel / serial conversion circuit which converts parallel data into serial data.

  The link controller LKC included in the high-speed I / F circuit block HB performs link layer processing such as packet processing. Specifically, the packet received via the physical layer circuit PHY is analyzed. Alternatively, a process for generating a packet to be transmitted via the physical layer circuit PHY may be performed. The link controller LKC can also perform communication error detection processing, transfer sequence control processing at the link layer level, and the like.

  In FIG. 1, the scan output line of the scan driver block SB is routed from the scan driver block SB to the scan driver pad arrangement region PR, bypassing the physical layer circuit PHY, as indicated by H1. Specifically, the scanning output line is wired to the scanning driver pad arrangement region PR through the link controller LKC without passing through the physical layer circuit PHY.

  For example, FIG. 2 shows an arrangement configuration of a comparative example. In the comparative example of FIG. 2, the scan output line of the scan driver block SB is wired on the physical layer circuit PHY. In this case, as described above, the amplitude of the scanning signal of the scanning output line is about 10 to 20 V, which is very large. Therefore, when the voltage level of the scan output line changes, the change in the voltage level of the scan output line is transmitted as signal noise to the physical layer circuit PHY via a parasitic capacitor formed by an insulating film or the like. As a result, the physical layer circuit PHY (for example, a receiver circuit) may malfunction and cause a data transfer error or the like.

  In this regard, in the present embodiment of FIG. 1, the scan output line of the scan driver block SB is wired so as to bypass the physical layer circuit PHY. Therefore, it is possible to prevent the change in the voltage level of the scanning output line from being transmitted as signal noise to the physical layer circuit PHY.

  In FIG. 1, the high-speed I / F circuit block HB and the scan driver block SB are disposed along the first direction D1. Specifically, HB and SB are adjacently arranged along the D1 direction. When the direction orthogonal to the D1 direction is the second direction D2, the scan driver pad arrangement region PR is provided on the D2 direction side of the high-speed I / F circuit block HB and the scan driver block SB. In FIG. 1, the direction opposite to the D1 direction is the third direction D3, and the direction opposite to the D2 direction is the fourth direction D4.

  1, the scanning driver block SB is arranged at the end of the integrated circuit device 10, so that the high-speed I / F circuit block HB is not arranged at the end of the integrated circuit device 10. It will be over.

  However, in the arrangement relationship of FIG. 1, it is necessary to wire a large number of scan output lines from the scan driver block SB to the scan driver pad arrangement region PR on the D2 direction side. Specifically, in order to prevent these scan output lines from crossing each other, after the scan output lines are wired along the direction D1, the direction is changed in the direction D2, and the scan driver lines are arranged in the scan driver pad arrangement region PR. It is necessary to wire. Therefore, if the scanning output line is wired without taking any signal noise into consideration, the scanning output line is wired on the physical layer circuit PHY as in the comparative example of FIG.

  In this regard, in the present embodiment, the wiring of the scanning output line is devised even when the scanning driver block SB, the high-speed I / F circuit block HB, and the scanning driver pad arrangement region PR are arranged as shown in FIG. This prevents the scanning output line from being wired on the physical layer circuit PHY. Therefore, it is possible to achieve both efficient wiring of a large number of scanning output lines from the scanning driver block SB and reduction of adverse effects of signal noise.

  In FIG. 1, the link controller LKC is arranged on the D2 direction side of the physical layer circuit PHY. Specifically, PHY and LKC are adjacently arranged along the D2 direction. With such an arrangement, the signal line between the physical layer circuit PHY and the link controller LKC can be connected by a short path, and the layout efficiency can be improved. In particular, since the operating frequency of the signal line between the physical layer circuit PHY and the link controller LKC is high, a signal transmission error can be prevented by connecting to such a short path.

  In FIG. 1, paying attention to the presence of the link controller LKC arranged on the D2 direction side of the physical layer circuit PHY in this way, the scanning output line from the scanning driver block SB is wired on the link controller LKC. If the scanning output lines are wired by effectively utilizing the wiring area on the link controller LKC in this way, the layout efficiency can be improved, and the width of the integrated circuit device 10 in the D2 direction due to the wiring area of the scanning output lines. Can be prevented from becoming large. Therefore, it is possible to achieve both the reduction of the chip area by improving the layout efficiency and the reduction of the adverse effects of signal noise.

2. Relationship with Logic Circuit Block FIG. 3A shows a detailed arrangement configuration example of the integrated circuit device 10. In FIG. 3A, the integrated circuit device 10 further includes a logic circuit block LB.

  The logic circuit block LB receives data received by the high-speed I / F circuit block HB. That is, data received by the physical layer circuit PHY using the differential signal and extracted (analyzed) by the packet analysis circuit of the link controller LKC is received. The logic circuit block LB controls the scan driver block SB. That is, various timings such as scanning start timing of scanning lines by the scanning driver block SB are controlled. The logic circuit block LB can control the high-speed I / F circuit block HB and a data driver block described later. The logic circuit block LB can be formed by automatic placement / wiring using, for example, a gate array (G / A).

  In FIG. 3, the high-speed I / F circuit block HB is disposed between the logic circuit block LB and the scan driver block SB. Specifically, for example, the logic circuit block LB and the high-speed I / F circuit block HB are arranged adjacently along the D1 direction, and the high-speed I / F circuit block HB and the scan driver block SB are also arranged adjacently along the D1 direction.

  With the arrangement as shown in FIG. 3A, the signal line between the high-speed I / F circuit block HB (link controller LKC) and the logic circuit block LB can be connected by a short path. Therefore, layout efficiency can be improved and signal skew between the high-speed I / F circuit block HB and the logic circuit block LB can be reduced.

  In the logic circuit block LB, a large number of I / O signal lines from the I / O pad region are wired from the D3 direction side along the D1 direction. As will be described later, data driver blocks are arranged on the D3 direction side of the logic circuit block LB, and a large number of global lines are wired along the D1 direction on these data driver blocks. Thus, a large number of signal lines such as global lines and I / O signal lines are wired on the D3 direction side of the logic circuit block LB. Therefore, when the high-speed I / F circuit block HB is arranged on the D3 direction side of the logic circuit block LB, the high-speed I / F circuit block HB may malfunction due to noise from these signal lines.

  In this regard, in FIG. 3, since the high-speed I / F circuit block HB is disposed on the D1 direction side of the logic circuit block LB, it is possible to prevent malfunction due to noise from signal lines such as the global lines as described above. Further, since the scanning driver block SB is arranged on the D1 direction side of the high-speed I / F circuit block HB, the high-speed I / F circuit block HB is not arranged at the end (right end) of the integrated circuit device 10. . Accordingly, it is possible to prevent an increase in the contact resistance of the pad caused by disposing the high-speed I / F circuit block HB at the end, and it is possible to prevent deterioration in signal quality of high-speed serial transfer.

  If the high-speed I / F circuit block HB is arranged between the logic circuit block LB and the scan driver block SB as described above, the noise of the scan output line is transmitted to the physical layer circuit PHY, which may cause a malfunction or the like. There is. In this regard, in FIG. 3A, since the scanning output line is wired as indicated by H3, such a situation can be prevented.

  When the logic circuit block LB and the link controller LKC are adjacently arranged along the direction D1 as shown in FIG. 3A, the logic circuit block LB and the link controller LKC are integrated as shown in FIG. It is desirable to form (integrate) and form by automatic placement and wiring. Specifically, for example, the net list of the logic circuit block LB and the net list of the link controller LKC are integrated to create one net list. Then, using the created netlist and a known automatic placement / wiring tool, automatic placement / wiring is executed for the circuit block in which the logic circuit block LB and the link controller LKC are integrated. Specifically, automatic placement / wiring is performed by a gate array (G / A) method using a plurality of base cells.

  In this way, the main logic portion of the integrated circuit device 10 can be formed by, for example, one automatic placement / wiring, so that the design efficiency and work efficiency can be improved. In addition, if integrated and automatic placement and wiring are performed in this way, signal skew and jitter between the logic circuit block LB and the link controller LKC can be optimally reduced.

  The arrangement configuration of the logic circuit block LB, the physical layer circuit PHY, the link controller LKC, and the scan driver block SB is not limited to FIG. 3A, and various modifications can be made. For example, an arrangement configuration as shown in FIG. In FIG. 4, at least the physical layer circuit PHY among the high-speed I / F circuit blocks is arranged on the D4 direction side of the logic circuit block LB (or data driver block). Specifically, for example, a receiver circuit (or transmitter circuit) of the physical layer circuit PHY is arranged on the D4 direction side of the logic circuit block LB (or data driver block). For example, a receiver circuit is arranged in the I / O region on the D4 direction side of the logic circuit block LB. In this way, the length of the integrated circuit device in the direction D1 can be shortened, and the chip area can be reduced.

  In the link controller LKC, a shield line may be provided below the scan output line of the scan driver block SB passing over the link controller LKC. For example, a shield line formed of a metal layer below the metal layer forming the scan output line is wired.

  For example, FIG. 5 shows a layout example of shield lines. In FIG. 5, the scan output line (scan driver global line) GLS from the scan driver block SB passes over the link controller LKC and is wired to the scan driver pads Pn, Pn + 1, Pn + 2,. In the link controller LKC, shield lines SDL1, SDL2, SDL3,... Are wired below these scanning output lines GLS. If such a shield line is wired, it is possible to prevent noise due to a change in the voltage level of the scanning output line GLS from being transmitted to the circuits and signal lines in the link controller LKC by the coupling capacitance. As a result, malfunction of these circuits can be prevented.

3. Common Voltage Line FIGS. 6A and 6B show an example of a display panel 300 on which the integrated circuit device 10 (display driver) of this embodiment is mounted. The display panel 300 includes an array substrate 310 (array glass substrate) and a counter substrate 320 (counter glass substrate). The array substrate 310 is formed with a TFT array portion 312 in which TFTs and pixel electrodes are arranged in a matrix. A counter electrode 322 is formed on the counter substrate 320. Liquid crystal is sealed between the array substrate 310 and the counter substrate 320. The integrated circuit device 10 is mounted on the array substrate 310 by COG (Chip On Glass) using, for example, bumps (gold bumps, resin core bumps) or the like.

  6A and 6B, the panel common voltage line (counter voltage line) for supplying the common voltage (counter electrode voltage) extends along the periphery of the TFT array portion 312 of the array substrate 310. Wired. Specifically, the panel common voltage line is wired from the common voltage pad PC1 provided at the left end of the integrated circuit device 10 (IC) along the left edge, the upper edge, and the right edge of the array substrate 310. It is connected to a common voltage pad PC2 provided at the right end of the device 10. The panel common voltage line is electrically connected to the counter electrode 322 of the counter substrate 320, for example, at an arbitrary position indicated by B1. Thereby, a common voltage can be supplied to the counter electrode 322.

  In FIG. 6A, the panel common voltage line is not wired below the integrated circuit device 10, but in FIG. 6B, the panel common voltage line is wired below the integrated circuit device 10.

  As shown in FIG. 6C, a data line (source line) is connected to the source of the TFT (thin film transistor), and a scanning line (gate line) is connected to the gate of the TFT. Data signals and scanning signals are supplied to these data lines and scanning lines. One end of a liquid crystal capacitor CL formed of a liquid crystal element is connected to the drain of the TFT, and a common voltage is supplied to the other end of the liquid crystal capacitor CL. Further, one end of the auxiliary capacitor CP is connected to the drain of the TFT, and a common voltage is supplied to the other end of the auxiliary capacitor CP. When such an auxiliary capacitor CP is used, a panel common voltage line is also wired to the TFT array portion 312 of FIGS. 6 (A) and 6 (B).

  A voltage that is the difference between the gradation voltage and the common voltage VCOM is applied to the liquid crystal element. Therefore, if the common voltage VCOM generated by the display driver does not reach the desired voltage due to parasitic resistance or the like, the voltage applied to the liquid crystal element also does not reach the desired voltage, so that the display quality deteriorates. . Therefore, in order to prevent such display quality deterioration, it is important to reduce the parasitic resistance of the common voltage line as much as possible.

4). As described above, the high-speed I / F circuit is susceptible to external noise. On the other hand, when the parasitic resistance of the common voltage line increases, the display quality of the display panel deteriorates. Therefore, it is desirable to employ the layout method described below.

  For example, in FIG. 7A, the integrated circuit device 10 includes a common voltage generation circuit VCB, at least one data driver block DB, and a physical layer circuit PHY that constitutes a high-speed I / F circuit block HB.

  In FIG. 7A, the direction from the first side SD1, which is the short side of the integrated circuit device 10, toward the third side SD3 facing the first direction D1 is defined as a first direction D1, and the direction opposite to D1 is defined as a third direction. D3. A direction from the second side SD2 which is the long side of the integrated circuit device 10 to the fourth side SD4 facing the second side D2 is a second direction D2, and a direction opposite to D2 is a fourth direction D4. In FIG. 7A, the left side of the integrated circuit device 10 is the first side SD1 and the right side is the third side SD3. However, the left side is the third side SD3 and the right side is the first side. SD1 may be used.

  The common voltage generation circuit VCB generates a common voltage VCOM that is applied to the counter electrode of the display panel. Specifically, for example, the common voltage VCOM whose polarity is inverted every scanning period is generated.

  In FIG. 7A, first and second common voltage pads PC1 and PC2 are provided. The common voltage pad PC1 is disposed on the D3 direction side of the data driver block DB, and the common voltage pad PC2 is disposed on the D1 direction side of the data driver block DB. Specifically, the common voltage pad PC1 is disposed at the left end of the integrated circuit device 10, and the common voltage pad PC2 is disposed at the right end of the integrated circuit device 10.

  The first and second differential input pads PP and PM for inputting the first and second signals DP and DM constituting the differential signal from the outside are connected to the D4 direction side (host side) of the physical layer circuit PHY. ). A common voltage line VCL (in-chip common voltage line) that connects the common voltage pads PC1 and PC2 is wired along the direction D1 from the common voltage pad PC1 to PC2. Specifically, in the arrangement region of the physical layer circuit PHY, wiring is performed along the D1 direction on the D2 direction side of the PHY. That is, the common voltage line VCL wired along the D1 direction from the common voltage pad PC1 is wired along the D2 direction on the D3 direction side of the PHY so as to change the direction and bypass the physical layer circuit PHY. Next, wiring is performed along the D1 direction on the D2 direction side of the physical layer circuit PHY, and wiring is performed along the D4 direction on the D1 direction side of the PHY. Then, it is connected to the common voltage pad PC2.

  In FIG. 7A, the common voltage line VCL is wired along the D1 direction on the D4 direction side of the data driver block DB in the arrangement region of the data driver block DB. That is, the common voltage line VCL is wired along the direction D1 between the host-side side SD2 of the integrated circuit device 10 and the data driver block DB.

  In FIG. 7B, the common voltage line VCL is wired along the D1 direction on the D2 direction side of the link controller LKC. Specifically, the common voltage line VCL is wired along the D2 direction on the D3 direction side of the physical layer circuit PHY and the link controller LKC. The D2 direction side of the link controller LKC is wired along the D1 direction, and the D1 direction side of the physical layer circuit PHY and link controller LKC is wired along the D4 direction and connected to the common voltage pad PC2.

  The common voltage generation circuit VCB is disposed on the D3 direction side of the data driver block DB. The common voltage generation circuit VCB may be arranged on the D1 direction side of the data driver block DB. Further, as shown in FIG. 7C, the common voltage line VCL can be modified in such a manner that the common voltage line VCL is wired along the D1 direction on the D2 direction side of the data driver block DB in the arrangement region of the data driver block DB.

  As shown in FIGS. 7A to 7C, in this embodiment, the common voltage line VCL connects the common voltage pads PC1 and PC2 in the chip of the integrated circuit device 10.

  For example, in FIG. 6A, if the common voltage pads PC1 and PC2 are not electrically connected in the chip of the integrated circuit device 10, the parasitic resistance value of the panel common voltage line at the position indicated by B2 is indicated by B3. It becomes higher than the parasitic resistance value at the position. Accordingly, the parasitic resistance value becomes allan balance, and unbalance occurs in the time until the common voltage reaches the desired voltage, so that the display quality is deteriorated.

  In this regard, in the present embodiment, the common voltage pads PC1 and PC2 are electrically connected by the common voltage line VCL, so that the parasitic resistance value of the common voltage line at the position B2 in FIG. The parasitic resistance values at the positions can be made substantially equal. Accordingly, it is possible to reduce display quality deterioration caused by an imbalance of parasitic resistance values. That is, even when the panel common voltage line is not wired below the integrated circuit device 10 as shown in FIG. 6A, the common voltage line VCL in the integrated circuit device 10 causes the case of FIG. Similarly, the common voltage line is wired in a ring shape at the peripheral edge of the array substrate 310. Therefore, it is possible to make the parasitic resistance values uniform at each position of the common voltage line. In particular, as shown in FIG. 6C, when a common voltage line for a panel is also wired to the TFT array portion 312 for the auxiliary capacitor CP, if an imbalance occurs in the parasitic resistance value of the common voltage line, display unevenness, etc. May occur. In this respect, if the common voltage pads PC1 and PC2 are connected to each other inside the integrated circuit device 10 by the common voltage line VCL as in the present embodiment, such uneven display can be prevented.

  In the present embodiment, the common voltage line VCL is wired so as to avoid the differential signal line that connects the physical layer circuit PHY and the differential input pads PP and PM. Therefore, for example, noise from the common voltage line VCL whose voltage changes every horizontal scanning period can be prevented from being superimposed on the input signals DP and DM of the physical layer circuit PHY. That is, if the common voltage line VCL wired along the D1 direction from the common voltage pad PC1 is directly wired along the D1 direction in the physical layer circuit PHY, the common voltage line VCL and the differential input pad PP, The differential signal line from PM crosses. As a result, noise from the common voltage line VCL is superimposed on the differential signals DP and DM via a parasitic capacitor or the like, which may cause a problem such as a data transfer error.

  In this respect, in the present embodiment, the common voltage line VCL is wired so as to avoid the intersection with the signals DP and DM, and thus the above-described problem can be prevented.

  7A and 7B, the common voltage line VCL is wired along the D1 direction on the D4 direction side of the data driver block DB. Therefore, a large number of data signal lines from the data driver block DB and the common voltage line VCL do not cross each other. Therefore, it is possible to prevent such noise from a large number of data signal lines from being superimposed on the common voltage line VCL via the parasitic capacitor. As a result, it is possible to prevent a situation where the level of the common voltage VCOM fluctuates and display quality deteriorates.

  A signal line that operates at high speed is wired between the physical layer circuit PHY and the link controller LKC. Therefore, if the common voltage line VCL is wired between the physical layer circuit PHY and the link controller LKC, the noise of such a signal line operating at high speed may be transmitted to the common voltage line VCL, and display quality may deteriorate.

  In this regard, in FIG. 7B, the common voltage line VCL is not wired between the physical layer circuit PHY and the link controller LKC, but is wired on the D2 direction side of the link controller LKC. Accordingly, it is possible to prevent a situation in which the noise of the high-speed operation signal line between the physical layer circuit PHY and the link controller LKC is transmitted to the common voltage line VCL, or the noise of the common voltage line VCL is transmitted to the high-speed operation signal line. Display quality can be improved.

  When a common voltage line for a panel is wired below the integrated circuit device 10 as shown in FIG. 6B, the common voltage line for the panel is also common to the common voltage lines for FIGS. 7A to 7C. It is desirable to wire by the same method as the wiring method of the voltage line VCL. That is, it is desirable to wire the panel common voltage line along the D1 direction on the D2 direction side of the physical layer circuit PHY and the link controller LKC so as not to cross the differential signal lines from the differential input pads PP and PM. .

5. Detailed Layout of Integrated Circuit Device FIG. 8 shows a detailed layout example of the integrated circuit device 10. The integrated circuit device 10 of FIG. 8 is arranged along the direction D1, and includes a plurality of data driver blocks DB1 to DBJ for driving data lines, and first and second scan driver blocks for driving scanning lines. Includes SB1 and SB2. Further, a gradation voltage generation circuit block GB for generating a plurality of gradation voltages, a power supply circuit block PB for generating a power supply voltage, a high-speed I / F circuit block HB having a physical layer circuit PHY and a link controller LKC, A logic circuit block LB and a common voltage generation circuit VCB are included.

  Here, the logic circuit block LB receives the data received by the high-speed I / F circuit block HB. Then, the gradation adjustment data for adjusting the gradation voltage is transferred to the gradation voltage generation circuit block GB, or the power supply adjustment data for adjusting the power supply voltage is transferred to the power supply circuit block PB.

  In FIG. 8, the gradation voltage generation circuit block GB is disposed on the D3 direction side of the data driver blocks DB1 to DBJ. That is, it is arranged on the D3 direction side of the leftmost data driver block DB1. Similarly, the power supply circuit block PB is arranged on the D3 direction side of the data driver blocks DB1 to DBJ. That is, it is arranged on the D3 direction side of the leftmost data driver block DB1. The high-speed I / F circuit block HB and the logic circuit block LB are arranged on the D1 direction side of the data driver blocks DB1 to DBJ. That is, it is arranged on the D1 direction side of the rightmost data driver block DBJ.

  The gradation voltage generation circuit block GB is disposed between the first scan driver block SB1 and the data driver blocks DB1 to DBJ. The high-speed I / F circuit block HB is disposed between the second scan driver block SB2 and the data driver blocks DB1 to DBJ. The common voltage generation circuit VCB is disposed on the D4 direction side of the scan driver block SB1.

  In FIG. 8, local lines formed by lower wiring layers are wired between adjacent circuit blocks. On the other hand, between non-adjacent circuit blocks, a global line formed by a wiring layer above the local line is wired along the direction D1. The gradation global line for supplying the gradation voltage from the gradation voltage generation circuit block GB to the data drivers DB1 to DBJ and the power supply global line for supplying the power supply voltage from the power supply circuit block PB are data. The driver blocks DB1 to DBJ are wired along the direction D1.

  When the scan driver blocks SB1 and SB2 are arranged at both ends of the integrated circuit device 10 as shown in FIG. 8, it is also possible to arrange the scan driver pads for outputting the scan signals at both ends of the integrated circuit device 10. It is desirable considering the wiring efficiency. On the other hand, the data driver blocks DB1 to DBJ are arranged near the center of the integrated circuit device 10. Therefore, it is desirable to arrange the data driver pad from which the data signal is output near the center of the integrated circuit device 10 in consideration of wiring efficiency.

  For this reason, in FIG. 8, scan driver pad arrangement regions PR1 and PR2 are provided at both ends of the integrated circuit device 10, and a data driver pad arrangement region PR3 is provided between the scan driver pad arrangement regions PR1 and PR2. . Thus, the output lines of the scan driver blocks SB1 and SB2 and the output lines of the data driver blocks DB1 to DBJ are connected to the pads of the scan driver pad arrangement areas PR1 and PR2 and the pads of the data driver pad arrangement area PR3. Can be connected efficiently.

  In FIG. 8, the data driver blocks DB <b> 1 to DBJ are arranged near the center of the integrated circuit device 10. Therefore, it becomes possible to provide the data driver pad arrangement region PR3 in the empty space on the D2 direction side of the data driver blocks DB1 to DBJ, so that the empty space can be effectively used. The data signal lines on the panel connected to the pads of the data driver pad arrangement region PR3 are routed to the TFT array portion on the array substrate.

  In FIG. 8, the grayscale voltage generation circuit block GB and the power supply circuit block PB having a large circuit area are arranged on the D3 direction side of the data driver blocks DB1 to DBJ. A logic circuit block LB and a high-speed I / F circuit block HB having a large circuit area are arranged on the D1 direction side of the data driver blocks DB1 to DBJ. In this way, the empty space on the D2 direction side of the grayscale voltage generation circuit block GB and the power supply circuit block PB having a large circuit area, or the D2 direction side of the logic circuit block LB and the high-speed I / F circuit block HB. Scan driver pad placement regions PR1 and PR2 can be provided by utilizing the empty space. Accordingly, since the empty space can be effectively used to improve the wiring efficiency, the width of the integrated circuit device 10 in the D2 direction can be reduced. The scanning signal lines on the panel connected to the pads of the scanning driver pad arrangement regions PR1 and PR2 are wired to the TFT array portion on the array substrate. The panel common voltage lines are wired on the left and right sides of these scanning signal lines.

  In FIG. 8, the logic circuit block LB and the high-speed I / F circuit block HB are adjacently disposed along the direction D1. Therefore, the signal line of the data received by the high-speed I / F circuit block HB can be connected to the logic circuit block LB by a short path, and the layout efficiency can be improved. Modifications such as arranging the high-speed I / F circuit block HB (physical layer circuit) on the D4 direction side of the logic circuit block LB are also possible.

  In FIG. 8, the high-speed I / F circuit block HB is arranged on the D1 direction side of the data driver blocks DB1 to DBJ, and the high-speed I / F circuit block HB is not arranged in the arrangement area of the data driver blocks DB1 to DBJ. Therefore, the gradation global line and the power supply global line wired to the data driver blocks DB1 to DBJ do not have to pass over the high-speed I / F circuit block HB. Therefore, it is possible to prevent the adverse effect of noise from these global lines from reaching the high-speed I / F circuit block HB (physical layer circuit PHY), and to prevent malfunction of the high-speed I / F circuit block HB.

  For example, when the integrated circuit device 10 is COG mounted on a glass substrate (array substrate) using bumps, there is a problem that the contact resistance at the bumps at both ends of the integrated circuit device 10 increases. That is, since the integrated circuit device 10 and the glass substrate have different coefficients of thermal expansion, the stress (thermal stress) caused by the difference in the coefficient of thermal expansion is greater at both ends of the integrated circuit device 10 than at the center. For this reason, at both ends of the integrated circuit device 10, the contact resistance at the bumps increases with time. In particular, as the integrated circuit device 10 becomes slim and slender, the difference in stress between both ends and the center increases, and the increase in contact resistance at the bumps at both ends also increases.

  On the other hand, in the high-speed I / F circuit block HB, impedance matching is performed between the transmission side and the reception side in order to prevent signal reflection. Therefore, when the contact resistance at the pads PP and PM of the high-speed I / F circuit block HB increases, impedance matching may be lost, and the signal quality of high-speed serial transfer may be degraded. Therefore, in consideration of such contact resistance, it is desirable that the high-speed I / F circuit block HB is disposed as close to the central portion of the integrated circuit device 10 as possible.

  In this regard, in FIG. 8, the high-speed I / F circuit block HB is arranged not between the rightmost side of the integrated circuit device 10 but between the data driver block DBJ and the scan driver block SB2. Therefore, compared to the case where the high-speed I / F circuit block HB is arranged on the rightmost side, the increase in contact resistance at the bump can be suppressed within an allowable range. If the high-speed I / F circuit block HB is provided in the arrangement area of the data driver blocks DB1 to DBJ because the problem of contact resistance is too important, the high-speed I / F circuit is affected by the noise from the global line as described above. The performance of the block HB is lowered. According to the layout method of FIG. 8, the problem of performance degradation due to noise from the global line can be solved while suppressing the increase in contact resistance within an allowable range.

6). As shown in FIGS. 7A to 7C, when a long common voltage line VCL is wired along the direction D1 on the elongated integrated circuit device 10, noise from other signal lines is generated. If the voltage is transmitted to the common voltage line VCL, the display characteristics may be deteriorated. For example, in the case of FIGS. 7A and 7B, noise from a digital signal line input to a logic circuit block or the like may be transmitted to the common voltage line VCL. In the case of FIG. 7C, noise from the data signal line from the data driver block and the scanning signal line from the scanning driver block may be transmitted to the common voltage line VCL.

  Accordingly, in FIGS. 9A to 9C, a shield line is provided to prevent noise of other signal lines from being transmitted to the common voltage line VCL. For example, in FIG. 9A, the first shield line SLD1 formed of a wiring layer different from the common voltage line VCL and supplied with a given power supply potential (for example, VSS) is connected to the common voltage line VCL. The wirings are overlapped in a plan view. That is, the shield line SLD1 is provided between the common voltage line VCL and another signal line, and the shield line SLD1 is formed by a wiring layer between the wiring layer forming the common voltage line VCL and the wiring layer forming another signal line. Is formed. In this way, noise from other signal lines (digital signal line, data signal line, scanning signal line, etc.) is transmitted below the common voltage line VCL, and provided below the common voltage line VCL. The shielded wire SLD1 can be used for shielding.

In FIG. 9B, the second shield lines SLD2 and SLD3, which are formed of the same wiring layer as the common voltage line VCL and to which a given power supply potential (for example, VSS) is applied, are connected to the common voltage line VCL. Wired on both sides. That is, when the common voltage line VCL is wired along the D1 direction, the shield lines SLD2 and SLD3 are wired along the D1 direction in parallel with the common voltage line VCL at a predetermined interval. In this way, noise from other signal lines can be shielded by the shield lines SLD2 and SLD3 provided on both sides of the common voltage line VCL from being transmitted from both sides of the common voltage line VCL. In (B), in addition to the shield lines SLD2 and SLD3 on both sides, the lower shield line SLD1 is also wired. In this way, noise transmission to the common voltage line VCL can be shielded more efficiently.

  When other signal lines are wired above the common voltage line VCL, the shield lines SLD1, SLD2, and SLD3 may be wired as shown in FIG. That is, the shield line SLD1 is wired above the common voltage line VCL, and the shield lines SLD2 and SLD3 are wired on both sides of the common voltage line VCL.

  The shield method for the common voltage line VCL described with reference to FIGS. 7A to 7C avoids the physical layer circuit PHY by connecting the scan output line from the scan driver block SB2 as indicated by H4 in FIG. This is particularly effective when wired on the link controller LKC.

  That is, in H4 of FIG. 8, the common voltage line VCL is wired along the D1 direction on the D2 direction side of the link controller LKC, and is wired along the D4 direction on the D1 direction side of LKC. On the other hand, the scan output line is routed from the scan driver block SB along the direction D3, then changed in direction on the link controller LKC, routed along the direction D2, and input to the scan driver pad arrangement region PR2. . Therefore, as indicated by H4 in FIG. 8, the common voltage line VCL and the scanning output line intersect each other in the area on the D2 direction side and the area on the D1 direction side of the link controller LKC.

  In this case, the voltage level of the scanning output line changes every predetermined cycle with an amplitude of 10 to 20V. Therefore, the signal noise caused by the change in the voltage level of the scanning output line is transmitted to the common voltage line VCL through the parasitic capacitor, and the display characteristics may be deteriorated.

  Even in such a case, if the shield method described with reference to FIGS. 7A to 7C is employed, the change in the voltage level of the scanning output line is blocked by the shield lines SLD1 to SLD3 and the like. Therefore, the voltage is not transmitted to the common voltage line VCL. Further, since the common voltage line VCL and the scan output line do not need to pass over the physical layer circuit PHY, malfunction of the physical layer circuit PHY can be prevented. As a result, it is possible to achieve both prevention of display characteristic deterioration due to noise superposition on the common voltage line VCL and prevention of malfunction of the physical layer circuit PHY.

7). Circuit Configuration Example of Integrated Circuit Device FIG. 10 shows a circuit configuration example of the integrated circuit device (display driver) of this embodiment. Note that the integrated circuit device of the present embodiment is not limited to the circuit configuration of FIG. 10, and various modifications such as omitting some of the components or adding other components are possible.

  The display panel includes a plurality of data lines (source lines), a plurality of scanning lines (gate lines), and a plurality of pixels specified by the data lines and the scanning lines. A display operation is realized by changing the optical characteristics of the electro-optic element (liquid crystal element in a narrow sense) in each pixel region. This display panel can be constituted by an active matrix type panel using switching elements such as TFT and TFD. The display panel may be a panel other than the active matrix system, or a panel other than the liquid crystal panel (organic EL panel or the like).

  The memory 20 (display data RAM) stores image data. The memory cell array 22 includes a plurality of memory cells and stores image data (display data) for at least one frame (one screen). The row address decoder 24 (MPU / LCD row address decoder) performs a decoding process on the row address and performs a word line selection process of the memory cell array 22. A column address decoder 26 (MPU column address decoder) performs a decoding process on the column address and performs a selection process of a bit line of the memory cell array 22. The write / read circuit 28 (MPU write / read circuit) performs image data write processing to the memory cell array 22 and image data read processing from the memory cell array 22.

  The logic circuit 40 (driver logic circuit) generates a control signal for controlling display timing, a control signal for controlling data processing timing, and the like. The logic circuit 40 can be formed by automatic placement and routing such as a gate array (G / A).

  The control circuit 42 generates various control signals and controls the entire apparatus. Specifically, gradation adjustment data (γ correction data) for adjusting gradation characteristics (γ characteristics) is output to the gradation voltage generation circuit 110, or the power supply voltage is supplied to the power supply circuit 90. Outputs power adjustment data for adjustment. In addition, a write / read process to the memory using the row address decoder 24, the column address decoder 26, and the write / read circuit 28 is controlled. The display timing control circuit 44 generates various control signals for controlling the display timing, and controls reading of image data from the memory 20 to the display panel side. The host (MPU) interface circuit 46 implements a host interface that accesses the memory 20 by generating an internal pulse for each access from the host. The RGB interface circuit 48 realizes an RGB interface that writes moving image RGB data to the memory 20 using a dot clock. Note that only one of the host interface circuit 46 and the RGB interface circuit 48 may be provided.

  The data driver 50 is a circuit that generates a data signal for driving the data lines of the display panel. Specifically, the data driver 50 receives image data (gradation data) from the memory 20, and receives a plurality (for example, 256 levels) of gradation voltages (reference voltages) from the gradation voltage generation circuit 110. Then, a voltage corresponding to the image data is selected from the plurality of gradation voltages and is output to the data line of the display panel as a data signal (data voltage).

  The scan driver 70 is a circuit that generates a scan signal for driving the scan lines of the display panel. Specifically, a signal (enable input / output signal) is sequentially shifted in a built-in shift register, and a signal obtained by converting the level of the shifted signal is output as a scanning signal (scanning voltage) to each scanning line of the display panel. . The scan driver 70 includes a scan address generation circuit and an address decoder, the scan address generation circuit generates and outputs a scan address, and the address decoder performs a scan address decoding process to generate a scan signal. Also good.

  The power supply circuit 90 is a circuit that generates various power supply voltages. Specifically, the input power supply voltage and the internal power supply voltage are boosted by a charge pump method using a boosting capacitor and a boosting transistor included in a built-in boosting circuit. Then, the voltage obtained by the boosting is supplied to the data driver 50, the scan driver 70, the gradation voltage generation circuit 110, and the like.

  The gradation voltage generation circuit (γ correction circuit) 110 is a circuit that generates a gradation voltage and supplies it to the data driver 50. Specifically, the gradation voltage generation circuit 110 can include a ladder resistor circuit that divides resistance between the high potential side power source and the low potential side power source and outputs the gradation voltage to the resistance division node. In addition, a gradation register unit in which gradation adjustment data is written, a gradation voltage setting circuit that variably sets (controls) the gradation voltage output to the resistance division node based on the written gradation adjustment data, and the like. Can be included.

  The high-speed I / F circuit 200 (serial interface circuit) is a circuit that realizes high-speed serial transfer via a serial bus. Specifically, high-speed serial transfer with the host (host device) is realized by current driving or voltage driving the differential signal line of the serial bus. FIG. 11A shows a configuration example of the high-speed I / F circuit 200.

  The physical layer circuit 210 (transceiver) is a circuit for receiving and transmitting data (packets) and clocks using differential signals (differential data signals and differential clock signals). Specifically, data and the like are transmitted and received by driving the differential signal lines of the serial bus with current or voltage. The physical layer circuit 210 can include a clock receiver circuit 212, a data receiver circuit 214, a transmitter circuit 216, and the like.

  The link controller 230 performs processing of a link layer (or transaction layer) that is an upper layer of the physical layer. Specifically, the link controller 230 can include a packet analysis circuit 232. When receiving a packet from a host (host device) via the serial bus, the packet analysis circuit 232 analyzes the received packet. That is, the header and data of the received packet are separated and the header is extracted. The link controller 230 can include a packet generation circuit 234. The packet generation circuit 234 performs packet generation processing when a packet is transmitted to the host via the serial bus. Specifically, a header of a packet to be transmitted is generated, and the packet is assembled by combining the header and data. Then, the physical layer circuit 210 is instructed to transmit the generated packet.

  The driver I / F circuit 240 performs an interface process between the high-speed I / F circuit 200 and an internal circuit of the display driver. Specifically, the driver I / F circuit 240 generates host interface signals including an address 0 signal A0, a write signal XWR, a read signal XRD, a parallel data signal PDATA, a chip select signal XCS, and the like, and generates an internal circuit of the display driver. (Host interface circuit 46).

  In FIG. 11B, the physical layer circuit 220 is built in the host device, and the physical layer circuit 210 is built in the display driver. Reference numerals 212, 214, and 226 denote receiver circuits, and reference numerals 216, 222, and 224 denote transmitter circuits. The operation of these receiver circuits 212, 214, 226 and transmitter circuits 216, 222, 224 can be enabled or disabled by enable signals ENBH, ENBC.

  The host-side clock transmitter circuit 222 outputs differential clock signals CKP and CKM. The client-side clock receiver circuit 212 performs differential amplification of the differential clock signals CKP and CKM, and outputs the obtained clock CKC to the subsequent circuit.

  The host-side data transmitter circuit 224 outputs differential data signals DP and DM. The data receiver circuit 214 on the client side performs differential amplification of the differential data signals DP and DM, and outputs the obtained data DATAC to a subsequent circuit. In FIG. 11B, data can also be transferred from the client side to the host side using the data transmitter circuit 216 on the client side and the data receiver circuit 226 on the host side.

  The configuration of the physical layer circuit 210 is not limited to FIGS. 11A and 11B, and various modifications can be made. For example, the physical layer circuit 210 can include a serial / parallel conversion circuit, a parallel / serial conversion circuit, etc. (not shown). Alternatively, a PLL (Phase Locked Loop) circuit, a bias voltage generation circuit, or the like may be included. Further, the differential signal line of the serial bus may have a multi-channel configuration. The physical layer circuit 210 includes at least one of a receiver circuit and a transmitter circuit. For example, the physical layer circuit 210 may be configured not to include a transmitter circuit. Further, the sampling clock may be generated based on the received data without providing the clock receiver circuit.

8). Elongated Integrated Circuit Device FIG. 12 shows an arrangement example of the integrated circuit device 10. The integrated circuit device 10 includes first to Nth circuit blocks CB1 to CBN (N is an integer of 2 or more) arranged along the direction D1. The integrated circuit device 10 also includes an output-side I / F region 12 (first interface region in a broad sense) provided along the side SD4 on the D2 direction side of the first to Nth circuit blocks CB1 to CBN. Further, it includes an input-side I / F area 14 (second interface area in a broad sense) provided along the side SD2 on the D4 direction side of the first to Nth circuit blocks CB1 to CBN. More specifically, the output-side I / F area 12 is arranged on the D2 direction side of the circuit blocks CB1 to CBN without using, for example, other circuit blocks. When the integrated circuit device 10 is used as an IP (Intellectual Property) core and incorporated in another integrated circuit device, the output-side I / F region, the input-side I / F region (first and second I / Os) It is also possible to adopt a configuration in which at least one of (regions) 12 and 14 is not provided.

  The output side (display panel side) I / F area 12 is an area serving as an interface with the display panel, and can include various elements such as a pad, an output transistor connected to the pad, and a protection element. Specifically, an output transistor for outputting a data signal to the data line or a scanning signal to the scanning line can be included. In the case where the display panel is a touch panel, an input transistor may be included.

  The input side (host side) I / F area 14 is an area serving as an interface with a host (MPU, image processing controller, baseband engine), and is a pad or an input (input / output) transistor connected to the pad. Various elements such as an output transistor and a protection element can be included. Specifically, an input transistor for inputting a signal (digital signal) from the host, an output transistor for outputting a signal to the host, and the like can be included.

  Note that an output-side I / F region or an input-side I / F region along the short sides SD1 and SD3 may be provided. Further, bumps or the like serving as external connection terminals may be provided in the I / F (interface) regions 12 and 14, or may be provided in other regions (first to Nth circuit blocks CB1 to CBN). In the case where it is provided in a region other than the I / F regions 12 and 14, it is realized by using a small bump technology (such as a bump technology using a resin as a core) other than the gold bump.

  The first to Nth circuit blocks CB1 to CBN can include at least two (or three) different circuit blocks (circuit blocks having different functions). Taking the case where the integrated circuit device 10 is a display driver as an example, the circuit blocks CB1 to CBN include at least two blocks of a data driver, a memory, a scan driver, a logic circuit, a gradation voltage generation circuit, and a power supply circuit. be able to. More specifically, the circuit blocks CB1 to CBN can include at least a data driver block and a logic circuit block, and can further include a grayscale voltage generation circuit block. In the case of a built-in memory type, a memory block can be included.

  FIGS. 13A and 13B show detailed examples of the planar layout of the integrated circuit device 10. 13A and 13B, first to Nth circuit blocks CB1 to CBN are first to fourth memory blocks MB1 to MB4 (first to Ith memory blocks in a broad sense). I is an integer of 2 or more. The first to fourth data driver blocks DB1 to DB4 (first in a broad sense, the first to fourth memory blocks MB1 to MB4) are arranged adjacent to each other along the direction D1. To I-th data driver block). Specifically, the memory block MB1 and the data driver block DB1 are arranged adjacently along the D1 direction, and the memory block MB2 and the data driver block DB2 are arranged adjacently along the D1 direction. The image data (display data) used by the data driver block DB1 to drive the data lines is stored in the adjacent memory block MB1, and the image data used by the data driver block DB2 to drive the data lines is adjacent. Memory block MB2 stores it.

  13A and 13B, scan driver blocks SB1 and SB2 are arranged at both ends of the integrated circuit device 10. It should be noted that only one of these scan driver blocks SB1 and SB2 can be provided, or a modification can be made without providing SB1 and SB2.

  In FIG. 13A, the grayscale voltage generation circuit block GB and the power supply circuit block PB2 are arranged on the D3 direction side of the data driver blocks DB1 to DB4 (memory blocks MB1 to MB4). A logic circuit block LB and a high-speed I / F circuit block HB are arranged on the D1 direction side of the data driver blocks DB1 to DB4 (MB1 to MB4). The gradation voltage generation circuit block GB is disposed between the power supply circuit block PB2 and the data driver blocks DB1 to DB4 (MB1 to MB4). The logic circuit block LB and the high-speed I / F circuit block HB are adjacently arranged in the direction D1. An information storage block ISB is provided on the D4 direction side of the logic circuit block LB.

  In FIG. 13A, the elongated power circuit block PB1 is connected between the circuit blocks CB1 to CBN (data driver blocks DB1 to DB4) and the input-side I / F area 14 (second interface area) D1. Arranged along the direction. The power supply circuit block PB1 is a circuit block having a long side in the D1 direction, a short side in the D2 direction, and a very narrow width in the D2 direction (an elongated circuit block having a width of WB or less). The power supply circuit block PB1 can include a boosting transistor of a boosting circuit that boosts a voltage by a charge pump, a boosting control circuit, and the like. On the other hand, the power supply circuit block PB2 includes a power supply register section in which power supply adjustment data for adjusting the power supply voltage is written, a regulator that adjusts the voltage boosted by the booster circuit that boosts the voltage by the charge pump, and the like. it can.

  On the other hand, in FIG. 13B, the gradation voltage generation circuit block GB and the logic circuit block LB are adjacently arranged. Data driver blocks DB1 to DB4 (MB1 to MB4) are arranged between the power supply circuit block PB and the gradation voltage generation circuit block GB and the logic circuit block LB. This makes it possible to input the gradation voltage setting signal from the logic circuit block LB to the gradation voltage generation circuit block GB through a short path.

  In FIG. 13B, the high-speed I / F circuit block HB (physical layer circuit) is arranged on the D4 direction side of the logic circuit block LB. In this way, a differential input signal from the differential input pad can be input to the high-speed I / F circuit block HB via a short path, and a signal from the high-speed I / F circuit block HB can be input to the logic circuit block LB via a short path. You can enter.

  Note that the layout arrangement of the integrated circuit device 10 of the present embodiment is not limited to FIGS. 13 (A) and 13 (B). For example, the number of memory blocks or data driver blocks may be 2, 3 or 5 or more, or the memory block or data driver block may be configured not to be divided into blocks. Further, a modification can be made so that the memory block and the data driver block are not adjacent to each other. Further, the memory block, the scan driver block, the power supply circuit block, the gradation voltage generation circuit block, or the like may be omitted. For example, when the memory is not built in, the memory block can be omitted, and when the scan driver can be formed on the glass substrate of the display panel, the scan driver block can be omitted. Further, the gradation voltage generating circuit block can be omitted for a color super twisted nematic (CSTN) panel and a thin film diode (TFD) panel. Further, a circuit block having a very narrow width in the D2 direction (elongated circuit block of WB or less) may be provided between the circuit blocks CB1 to CBN and the output-side I / F region 12 or the input-side I / F region 14. The circuit blocks CB1 to CBN may include circuit blocks in which different circuit blocks are arranged in multiple stages in the D2 direction. For example, the scan driver circuit and the power supply circuit may be configured as one circuit block.

  FIG. 14A shows an example of a cross-sectional view of the integrated circuit device 10 along the direction D2. Here, W1, WB, and W2 are the widths in the D2 direction of the output side I / F region 12, the circuit blocks CB1 to CBN, and the input side I / F region 14, respectively. The widths W1, WB, and W2 are the widths (maximum widths) of the transistor formation regions (bulk region and active region) in the output side I / F region 12, circuit blocks CB1 to CBN, and input side I / F region 14, respectively. Yes, it does not include the bump formation area. W is the width of the integrated circuit device 10 in the direction D2. In this case, for example, a relationship of W1 + WB + W2 ≦ W <W1 + 2 × WB + W2 is established. Alternatively, since W1 + W2 <WB holds, the relationship of W <2 × WB holds.

  In the arrangement method of FIG. 14B, two or more circuit blocks having a wide width in the D2 direction are arranged along the D2 direction. Specifically, the data driver block and the memory block are arranged along the direction D2.

  For example, in FIG. 14B, image data from the host side is written into the memory block. The data driver block converts the digital image data written in the memory block into an analog data voltage, and drives the data lines of the display panel. Accordingly, the signal flow of the image data is in the direction D2. For this reason, in FIG. 14B, the memory block and the data driver block are arranged along the direction D2 in accordance with the flow of this signal.

  Here, the arrangement method of FIG. 14B has the following problems.

  First, in an integrated circuit device such as a display driver, a reduction in chip size is required for cost reduction. However, if a fine process is employed and the integrated circuit device is simply shrunk to reduce the chip size, not only the short side direction but also the long side direction is reduced, and mounting becomes difficult due to the narrow pitch.

  Secondly, in the display driver, the configuration of the memory and data driver varies depending on the type of display panel (amorphous TFT, low-temperature polysilicon TFT), the number of pixels (QCIF, QVGA, VGA), product specifications, and the like. Therefore, in the arrangement method of FIG. 14B, even if the pad pitch, the memory cell pitch, and the data driver cell pitch match in a certain product, these pitches do not match if the configuration of the memory or data driver changes. . If the pitches do not match, it becomes necessary to form a useless wiring region for absorbing the pitch mismatch between the circuit blocks. As a result, the width of the integrated circuit device in the direction D2 is increased, the chip area is increased, and the cost is increased. On the other hand, in order to avoid such a situation, if the layout of the memory or data driver is changed so that the pad pitch and the cell pitch are aligned, the development period becomes longer, resulting in an increase in cost.

  On the other hand, in the arrangement method shown in FIGS. 12 to 13B, a plurality of circuit blocks CB1 to CBN are arranged along the direction D1. In FIG. 14A, a transistor (circuit element) can be arranged under the pad (bump) (active surface bump). In addition, signal lines between circuit blocks, between circuit blocks and I / F regions, and the like can be formed by global wiring formed in a layer above the local wiring (lower layer than the pad) that is a wiring in the circuit block. Therefore, the width W in the D2 direction can be narrowed while maintaining the length of the integrated circuit device 10 in the D1 direction, and a slim elongated chip can be realized.

  12 to 13B, the circuit blocks CB1 to CBN are arranged along the direction D1, so that it is possible to easily cope with a change in product specifications. In other words, since it is possible to design products with various specifications using a common platform, the design efficiency can be improved. For example, even when the number of pixels and the number of gradations of the display panel increase / decrease, it can be dealt with only by increasing / decreasing the number of blocks of the memory blocks and data driver blocks, the number of times of reading out image data in one horizontal scanning period, and the like. For example, when the scan driver can be formed on the display panel side, such as a low-temperature polysilicon TFT panel, it is only necessary to remove the scan driver block from the circuit blocks CB1 to CBN. When developing a product without a memory, the memory block can be removed. Even if the circuit block is removed in accordance with the specifications as described above, the influence of the circuit block on other circuit blocks can be minimized, so that the design efficiency can be improved.

  12 to 13B, the width (height) of each circuit block CB1 to CBN in the D2 direction can be unified to, for example, the width (height) of the data driver block or the memory block. When the number of transistors in each circuit block increases / decreases, the design can be made more efficient because it can be adjusted by increasing / decreasing the length of each circuit block in the D1 direction. For example, even when the configuration of the gradation voltage generation circuit block or the logic circuit block is changed and the number of transistors is increased or decreased, the length in the D1 direction of the gradation voltage generation circuit block or the logic circuit block is increased or decreased. Yes.

9. Grayscale Voltage Generation Circuit FIG. 15 shows a configuration example of the grayscale voltage generation circuit. The gradation voltage generation circuit includes a ladder resistor circuit 120, a gradation voltage setting circuit 130, and a control circuit 140.

  Here, the ladder resistor circuit 120 divides the resistance between the high potential side power supply (power supply voltage) VDDRH and the low potential side power supply (power supply voltage) VDDRL, and a plurality of resistance division nodes RT0 to RT255 have a plurality of resistance division nodes. The gradation voltages V0 to V255 are output.

  The control circuit 140 includes a gradation register unit 142 and an address decoder 144. In the gradation register unit 142, gradation adjustment data (data for adjusting gradation characteristics) from a logic circuit (logic circuit block) is written. The address decoder 144 decodes an address signal from the logic circuit and outputs a register address signal corresponding to the address signal. In the gradation register unit 142, gradation adjustment data is written to the register in which the register address signal from the address decoder 144 is active based on the latch signal from the logic circuit.

  The gradation voltage setting circuit 130 (gradation selector) variably sets (controls) the gradation voltage output to the resistance division nodes RT0 to RT255 based on the gradation adjustment data written in the gradation register unit 142. To do. Specifically, for example, the gradation voltage is variably set by variably controlling the resistance values of a plurality of variable resistance circuits included in the ladder resistance circuit 120.

  Note that the gradation voltage generation circuit is not limited to the configuration shown in FIG. 15, and various modifications can be made. Some of the components shown in FIG. 15 may be omitted or other components may be added. For example, a ladder resistor circuit for positive polarity and a ladder resistor circuit for negative polarity may be provided, or a circuit (voltage follower-connected operational amplifier) that performs impedance conversion of a gradation voltage signal may be provided. Alternatively, the gradation voltage generation circuit may include a selection voltage generation circuit and a gradation voltage selection circuit. In this case, the voltage divided by the ladder resistor circuit included in the selection voltage generation circuit is output as a plurality of selection voltages. Then, the gradation voltage selection circuit selects, for example, 256 (S in a broad sense) voltage in the case of 256 gradations according to the gradation adjustment data from the selection voltages from the selection voltage generation circuit. Select and output as gradation voltages V0 to V255.

  In FIG. 16A, the circuit blocks CB1 to CBN include a gradation voltage generation circuit block GB, data driver blocks DB1, DB2,..., And a logic circuit block LB. Here, the logic circuit block LB transfers gradation adjustment data for adjusting the gradation voltage to the gradation voltage generation circuit block GB. The gradation voltage generation circuit block GB generates a plurality of gradation voltages based on the transferred gradation adjustment data. For example, the gradation voltage generation circuit block GB adjusts the gradation voltage and outputs the adjusted gradation voltage.

  In FIG. 16A, the data driver blocks DB1, DB2,... Are arranged between the gradation voltage generation circuit block GB and the logic circuit block LB.

  16A, the data driver blocks DB1, DB2,... Can be arranged near the center of the integrated circuit device. Therefore, it becomes possible to arrange pads for data drivers (source drivers) using the empty space on the D2 direction side of the data driver blocks DB1, DB2,..., And to effectively use the empty space.

  Further, according to the layout method of FIG. 16A, the gradation voltage generation circuit block GB and the logic circuit block LB can be arranged on the left side and the right side of the data driver blocks DB1, DB2,. Accordingly, it becomes possible to arrange a scan driver (gate driver) pad or the like by using, for example, the empty space on the D2 direction side of the gradation voltage generating circuit block GB and the logic circuit block LB, and effective use of the empty space is possible. I can plan.

  In FIG. 16B, the logic circuit block LB is a grayscale voltage generation circuit block that time-divides grayscale adjustment data (grayscale voltage adjustment data) via n-bit (n is a natural number) grayscale transfer line GTL. Transferring to GB. For example, j-bit (j> n) gradation adjustment data is transferred (serially transferred) to the gradation register unit 142 of the gradation voltage generation circuit block GB in a time-sharing manner by n bits.

  That is, in order to improve display quality, it is desirable to set an optimum gradation characteristic (γ characteristic) according to the type of display panel. If the gradation characteristics can be adjusted to suit the characteristics of various display panels, the amount of gradation adjustment data becomes very large. Therefore, if the gradation adjustment data having such a large amount of data is written to the gradation register unit 142 all at once in parallel rather than in time division, the number of bits of the transfer line increases and the number of transfer lines increases. . In the layout method in which the data driver blocks DB1, DB2,... Are arranged between the gradation voltage generation circuit block GB and the logic circuit block LB, as the number of transfer lines increases, data driver control, power supply, and gradation voltage are increased. There is no room for the number of global lines to supply. As a result, the width of the integrated circuit device in the direction D2 increases by the number of gradation adjustment data transfer lines, making it difficult to realize a slim elongated chip.

  In this case, a method is also conceivable in which the gradation voltage generation circuit block GB and the logic circuit block LB are arranged adjacent to each other and gradation adjustment data is transferred using a local line connecting GB and LB. However, according to this method, the grayscale voltage generation circuit block GB and the logic circuit block LB are arranged to be biased to the left or right of the data driver blocks DB1, DB2,. Therefore, the empty area for arranging the scan driver pads and the like is also formed to be biased to the left or right of the data driver blocks DB1, DB2,..., And the layout efficiency is lowered.

  In this regard, the number of gradation transfer lines GTL can be reduced by transferring the gradation adjustment data in a time division manner as shown in FIG. As a result, there is room for wiring of other global lines, the width of the integrated circuit device in the D2 direction can be reduced, and a slim elongated chip can be realized. Also, empty areas for arranging the scan driver pads and the like are formed uniformly on the left side or the right side of the data driver blocks DB1, DB2,..., And the layout efficiency can be improved.

  Next, a specific method for transferring gradation adjustment data will be described. In FIG. 16B, the logic circuit block LB receives an address signal for specifying the register address of the gradation register unit 142 and a data signal for transferring the gradation adjustment data written to the specified register address. The data is output to the gradation voltage generation circuit block GB via the gradation transfer line GTL. Further, for example, a latch signal for taking in the data signal is output to the gradation voltage generation circuit block GB. In this case, for example, the logic circuit block LB outputs the address signal of the first bit pattern in a period other than the data valid period in which a valid data signal is output. In the register map of the gradation register unit 142, a register to which gradation adjustment data is written is mapped to a register address other than the register address corresponding to the address signal of the first bit pattern.

  FIG. 17A shows signal waveform examples of the address signals A3 to A0, the data signals D7 to D0, and the latch signal LAT.

  As shown in FIG. 17A, the logic circuit block LB has a bit pattern (Fh) = (1111) (in a broad sense) in a period TB other than the data valid period TA in which valid data signals D7 to D0 are output. The first bit pattern) address signals A3 to A0 are output. That is, the address signals A3 to A0 having a bit pattern in which all bits are “1” (first logic level in a broad sense) are output. “H” means hex display.

  On the other hand, the logic circuit block LB corresponds to the address signals A3 to A0 corresponding to the register addresses of the registers R0 to RI of the gradation register 142 and the gradation adjustment data written to the registers R0 to RI in the data valid period TA. Output data signals D7 to D0. A latch signal LAT for taking in the data signals D7 to D0 is output. That is, in the gradation register unit 142, based on the latch signal LAT (falling edge of LAT), the data signals D7 to D0 are transmitted to the registers specified by the register addresses of the address signals A3 to A0 among the registers R0 to RI. Gradation adjustment data is written. As a result, the gradation adjustment data DAR0, DAR1, DAR2,... Are written in the gradation register unit 142 in a time division manner. Note that the number of bits of the address signal and the data signal is not limited to 4 bits or 8 bits and is arbitrary.

  FIG. 17B shows a register map of the gradation register unit 142. In this register map, the register addresses (0h) = (0000), (1h) = (0001), (2h) = (0010)... Of the address signals A3 to A0 include the registers R0, R1, R2,. -Is mapped. The gradation adjustment data DARO, DAR1 set by the data signals D7 to D0 for the registers R0, R1, R2,... Mapped to the register addresses (0h), (1h), (2h). , DAR2... Are written. For example, DARO, DAR1, and DAR2 are data for setting the gradient in each section of the gradation characteristics.

  Specifically, a processing unit (CPU, MPU) outside the integrated circuit device issues a gradation adjustment command and outputs a parameter serving as gradation adjustment data to the integrated circuit device. In response to this, the logic circuit block LB writes the gradation adjustment data corresponding to the parameter to the registers R0 to RI of the gradation register unit 142 using the address signals A3 to A0 and the data signals D7 to D0. . As a result, the gradation characteristics can be adjusted from the outside, and the display quality of the display panel can be improved.

  Incidentally, when an electrostatic voltage is applied to a display panel or the like by an ESD immunity test (Electro Static Discharge Immunity Test) or the like, there is a possibility that noise is added to the latch signal LAT in the period TB of FIG. Then, in the period TB other than the data valid period TA, there is a possibility that the gradation adjustment data of the data signals D7 to D0 that are not valid is written to the register at the register address (Fh). Then, an unintended gradation voltage is generated. This causes problems such as an abnormal display state of the display panel. In particular, if the distance between the logic circuit block LB and the grayscale voltage generation circuit block GB is long as in the layout examples of FIGS. 16A and 16B, noise is likely to be applied to the signal, causing problems. It becomes easy.

  For this reason, in the register map of the gradation register unit 142 in FIG. 17B, for the register address corresponding to the address signal of the bit pattern (first bit pattern) of (Fh), the gradation register unit 142 The register is not mapped. Then, registers R0, R1, R2,... RI to which gradation adjustment data is written are registered for register addresses (0h), (1h), (2h),... (Eh) other than the register address of (Fh). Map. Specifically, when the register address of the address signals A3 to A0 is (Fh), the address decoder 144 in FIG. 15 does not output a valid register address signal. Further, the register of the gradation register unit 142 does not hold gradation adjustment data corresponding to the data signals D7 to D0.

  In this way, even when the noise is added to the latch signal LAT or the like in the period TB, the register is not mapped to the register address (Fh), so that erroneous gradation adjustment data is not written to the register. Absent. Therefore, it is possible to prevent a situation in which the display state of the display panel becomes abnormal due to the application of electrostatic voltage, and to provide an integrated circuit device or an electronic device with high ESD immunity withstand voltage.

  Note that the register address to which no register is mapped in the gradation register unit 142 is not limited to (Fh) = (1111) as shown in FIG. For example, the register address (0h) = (0000) of a bit pattern in which all bits of the address signal are “0” (second logic level in a broad sense) may be used.

10. Global Wiring Method In order to reduce the width of the integrated circuit device in the D2 direction, it is necessary to efficiently wire signal lines and power supply lines between circuit blocks arranged along the D1 direction. For this reason, it is desirable to wire signal lines and power supply lines between circuit blocks by a global wiring method.

  Specifically, in this global wiring method, between adjacent circuit blocks of the first to Nth circuit blocks CB1 to CBN, a wiring layer (I is an integer of 3 or more) lower than the wiring layer (I is an integer of 3 or more). For example, local lines formed of first to fourth aluminum wiring layers ALA, ALB, ALC, ALD) are wired. On the other hand, between non-adjacent circuit blocks among the first to Nth circuit blocks CB1 to CBN, a global line formed of a wiring layer (for example, the fifth aluminum wiring layer ALE) of the Ith layer or higher is adjacent. Wiring is performed along the direction D1 on the circuit blocks interposed between the circuit blocks that are not.

  FIG. 18 shows an example of global line wiring. In FIG. 18, driver global lines GLD for supplying driver control signals from the logic circuit block LB to the data driver blocks DB1 to DB3 are wired on the buffer circuits BF1 to BF3 and the row address decoders RD1 to RD3. That is, the driver global line GLD formed by the fifth aluminum wiring layer ALE, which is the top metal, is substantially straight along the D1 direction from the logic circuit block LB to the buffer circuits BF1 to BF3 and the row address decoders RD1 to RD3. Wired to The driver control signals supplied by these driver global lines GLD are buffered by the buffer circuits BF1 to BF3 and input to the data drivers DR1 to DR3 arranged on the D2 direction side of the buffer circuits BF1 to BF3. The

  In FIG. 18, a memory global line GLM for supplying at least a write data signal (or an address signal and a memory control signal) from the logic circuit block LB to the memory blocks MB1 to MB3 is wired along the direction D1. The That is, the memory global line GLM formed of the fifth aluminum wiring layer ALE is wired from the logic circuit block LB along the direction D1.

  More specifically, in FIG. 18, repeater blocks RP1 to RP3 are arranged corresponding to the memory blocks MB1 to MB3. These repeater blocks RP1 to RP3 include a buffer that buffers at least a write data signal (or an address signal or a memory control signal) from the logic circuit block LB and outputs the buffered data to the memory blocks MB1 to MB3. As shown in FIG. 18, the memory blocks MB1 to MB3 and the repeater blocks RP1 to RP3 are adjacently disposed along the direction D1.

  For example, when a write data signal, an address signal, and a memory control signal from the logic circuit block LB are supplied to the memory blocks MB1 to MB3 using the memory global line GLM, if these signals are not buffered, the signal rises. Waveform and falling waveform are dull. As a result, there is a possibility that the data writing time to the memory blocks MB1 to MB3 becomes long or a writing error occurs.

  In this regard, if repeater blocks RP1 to RP3 as shown in FIG. 18 are arranged adjacent to each memory block MB1 to MB3, for example, on the D1 direction side, these write data signals, address signals, and memory control signals are transmitted to the repeater blocks RP1 to RP1. The data is buffered by RP3 and input to each of the memory blocks MB1 to MB3. As a result, it is possible to reduce the dullness of the rising waveform and falling waveform of the signal, and it is possible to realize proper data writing to the memory blocks MB1 to MB3.

  In FIG. 18, the integrated circuit device includes a gradation voltage generation circuit block GB for generating gradation voltages. A gradation global line GLG (gradation voltage supply line) for supplying the gradation voltage from the gradation voltage generation circuit block GB to the data driver blocks DB1 to DB3 is wired along the direction D1. That is, the gradation global line GLG formed by the fifth aluminum wiring layer ALE is wired from the gradation voltage generation circuit block GB along the direction D1. The gradation voltage supply lines GSL1 to GSL3 for supplying the gradation voltages from the gradation global line GLG to the data drivers DR1 to DR3 are wired along the direction D2 in each of the data drivers DR1 to DR3.

  Further, in FIG. 18, the memory global line GLM is wired along the direction D1 between the gradation global line GLG and the driver global line GLD.

  That is, in FIG. 18, the buffer circuits BF1 to BF3 and the row address decoders RD1 to RD3 are arranged along the direction D1. By wiring the driver global line GLD along the D1 direction from the logic circuit block LB through the buffer circuits BF1 to BF3 and the row address decoders RD1 to RD3, the wiring efficiency can be greatly improved.

  Further, it is necessary to supply the grayscale voltage from the grayscale voltage generation circuit block GB to the data drivers DR1 to DR3. For this purpose, the grayscale global line GLG is wired along the direction D1.

  On the other hand, address signals, memory control signals, and the like are supplied to the row address decoders RD1 to RD3 through the memory global line GLM. Therefore, the memory global line GLM is preferably wired near the row address decoders RD1 to RD3.

  In this regard, in FIG. 18, the memory global line GLM is wired between the gradation global line GLG and the driver global line GLD. Accordingly, an address signal, a memory control signal, and the like from the memory global line GLM can be supplied to the row address decoders RD1 to RD3 through a short path. Further, the gradation global line GLG can be arranged substantially straight along the direction D1 above the memory global line GLM. Accordingly, it is possible to perform wiring without crossing the global lines GLG, GLM, and GLD by using a single aluminum wiring layer ALE, and wiring efficiency can be improved.

  In FIG. 18, the gradation transfer line GTL is wired along the D1 direction on the data driver blocks DB1 to DB3 by the global line. In this case, as described above, the gradation adjustment data is transferred in time division on the gradation transfer line GTL. Therefore, the number of gradation transfer lines GTL, which are global lines, can be reduced as compared with a method in which gradation adjustment data is transferred at a time using a parallel transfer line. Therefore, it is possible to cope with a case where the number of global lines GLD, GLM, and GLG for drivers, memories, and gradations increases and there is no room for global line wiring. Therefore, it is possible to prevent a situation in which the width of the integrated circuit device in the direction D2 increases due to the number of gradation transfer lines GTL, and the area of the integrated circuit device can be reduced.

  In FIG. 18, the power supply transfer line PTL is wired along the D1 direction on the data driver blocks DB1 to DB3 by a global line. The logic circuit block LB transfers the power supply adjustment data to the power supply circuit block PB2 in a time-sharing manner through the m-bit (m is a natural number) power supply transfer line PTL. The power supply transfer line PTL is also wired along the direction D1 by a global line. A power supply global line (not shown) for supplying the power supply voltage from the power supply circuit block PB2 to each circuit block is also wired along the direction D1.

  Further, the time division transfer of the power supply adjustment data can be realized by the same method as the time division transfer method of the gradation adjustment data described with reference to FIGS. That is, the power supply register block 38 and an address decoder (not shown) are provided in the power supply circuit block PB2. Then, the power adjustment data may be time-divisionally transferred via the power supply transfer line PTL and written to each register address of the power supply register unit 38 by the method described with reference to FIGS. 17A and 17B.

11. Block Division As shown in FIG. 19A, the display panel has a number of pixels in the vertical scanning direction (data line direction) of VPN = 320, and a number of pixels in the horizontal scanning direction (scanning line direction) of HPN = 240. Is a QVGA panel. Further, it is assumed that the bit number PDB of image (display) data for one pixel is 8 bits for each of R, G, and B, and PDB = 24 bits. In this case, the number of bits of image data necessary for displaying one frame of the display panel is VPN × HPN × PDB = 320 × 240 × 24 bits. Therefore, the memory of the integrated circuit device stores image data for at least 320 × 240 × 24 bits. The data driver also displays HPN = 240 data signals (data signals corresponding to 240 × 24 bits of image data) every horizontal scanning period (each scanning period of one scanning line). Output to the panel.

  In FIG. 19B, the data driver is divided into DBN = 4 data driver blocks DB1 to DB4. The memory is also divided into MBN = DBN = 4 memory blocks MB1 to MB4. That is, for example, four driver macro cells DMC1, DMC2, DMC3, and DMC4 in which a data driver block, a memory block, and a pad block are converted into macro cells are arranged along the direction D1. Accordingly, each data driver block DB1 to DB4 outputs HPN / DBN = 240/4 = 60 data signals to the display panel every horizontal scanning period. Each of the memory blocks MB1 to MB4 stores (VPN × HPN × PDB) / MBN = (320 × 240 × 24) / 4 bits of image data.

12 Reading multiple times in one horizontal scanning period In FIG. 19B, each of the data driver blocks DB1 to DB4 is 60 lines in one horizontal scanning period (60 × 3 = 180 assuming that R, G, and B are three lines). Output data signal. Therefore, it is necessary to read image data corresponding to 240 data signals for each horizontal scanning period from the memory blocks MB1 to MB4 corresponding to DB1 to DB4.

  However, if the number of bits of image data to be read for each horizontal scanning period increases, it is necessary to increase the number of memory cells (sense amplifiers) arranged in the D2 direction. As a result, the width W in the direction D2 of the integrated circuit device is increased, and the slimming of the chip is prevented. In addition, the word line WL becomes long, which causes a problem of WL signal delay.

  In order to solve such a problem, the image data stored in each of the memory blocks MB1 to MB4 is transferred from the memory blocks MB1 to MB4 to the data driver blocks DB1 to DB4 a plurality of times in one horizontal scanning period ( It is desirable to adopt a method of reading (RN times).

  For example, in FIG. 20, as indicated by A1 and A2, the memory access signal MACS (word selection signal) becomes active (high level) only RN = 2 times in one horizontal scanning period. Thus, image data is read from each memory block to each data driver block RN = 2 times in one horizontal scanning period. Then, the latch circuits of the data drivers DRa and DRb provided in the data driver block in FIG. 21 latch the read image data based on the latch signals LATa and LATb indicated by A3 and A4. The multiplexers of the data drivers DRa and DRb multiplex the latched image data, and the DRa and DRb D / A converters perform D / A conversion of the multiplexed image data. Then, the output circuits of the data drivers DRa and DRb output the data signals DATAa and DATAb obtained by the D / A conversion as indicated by A5 and A6. Thereafter, as shown at A7, the scanning signal SCSEL inputted to the gate of the TFT of each pixel of the display panel becomes active, and the data signal is inputted and held in each pixel of the display panel.

  In FIG. 20, the image data is read twice in the first horizontal scanning period, and the data signals DATAa and DATAb are output to the data signal output line in the same first horizontal scanning period. However, the image data is read and latched twice in the first horizontal scanning period, and the data signals DATAa and DATAb corresponding to the latched image data are supplied to the data signal output lines in the next second horizontal scanning period. It may be output. FIG. 20 shows the case where the number of times of reading RN = 2, but RN ≧ 3 may be possible.

  According to the method shown in FIG. 20, as shown in FIG. 21, image data corresponding to 30 data signals is read from each memory block, and each data driver DRa, DRb outputs 30 data signals. To do. As a result, 60 data signals are output from each data driver block. As described above, in FIG. 20, it is only necessary to read image data corresponding to 30 data signals from each memory block in one reading. Therefore, the number of memory cells and sense amplifiers in the direction D2 in FIG. 21 can be reduced as compared with the method of reading only once in one horizontal scanning period. As a result, the width of the integrated circuit device in the direction D2 can be reduced, and a slim and slender chip can be realized. In particular, the length of one horizontal scanning period is about 52 μsec in the case of QVGA. On the other hand, the memory read time is, for example, about 40 nsec, which is sufficiently shorter than 52 μsec. Therefore, even if the number of readings in one horizontal scanning period is increased from one to a plurality of times, the influence on the display characteristics is not so great.

  FIG. 19A shows a display panel of QVGA (320 × 240). If the number of readings in one horizontal scanning period is set to RN = 4, for example, it corresponds to a display panel of VGA (640 × 480). It is also possible to increase the degree of design freedom.

  The plurality of readings in one horizontal scanning period may be realized by a first method in which a row address decoder (word line selection circuit) selects a plurality of different word lines in each memory block in one horizontal scanning period. Alternatively, the same word line in each memory block may be realized by a second method in which a row address decoder (word line selection circuit) selects a plurality of times in one horizontal scanning period. Alternatively, it may be realized by a combination of both the first and second methods.

  In FIG. 21, the data driver block includes a plurality of data drivers DRa and DRb arranged side by side along the direction D1. Each data driver DRa, DRb includes a plurality of driver cells.

  When the word line WL1a of the memory block is selected and the first image data is read from the memory block as shown by A1 in FIG. 20, the data driver DRa is read based on the latch signal LATa shown by A3. The image data is latched, and the latched image data is multiplexed. Then, D / A conversion of the multiplexed image data is performed, and a data signal DATAa corresponding to the first read image data is output as indicated by A5.

  On the other hand, when the word line WL1b of the memory block is selected and the second image data is read from the memory block as shown by A2 in FIG. 20, the data driver DRb reads based on the latch signal LATb shown by A4. The latched image data is latched, and the latched image data is multiplexed. Then, D / A conversion of the multiplexed image data is performed, and a data signal DATAb corresponding to the second read image data is output as indicated by A6.

  In this way, each data driver DRa, DRb outputs 30 data signals corresponding to 30 pixels, so that 60 data signals corresponding to 60 pixels in total are output. It becomes like this.

  If a plurality of data drivers DRa and DRb are arranged (stacked) along the D1 direction as shown in FIG. 21, the width W in the D2 direction of the integrated circuit device is increased due to the size of the data driver. It can prevent the situation. The data driver has various configurations depending on the type of the display panel. Also in this case, according to the method of arranging a plurality of data drivers along the direction D1, data drivers having various configurations can be efficiently laid out. FIG. 21 shows a case where the number of data drivers arranged in the direction D1 is two, but the number of arranged data drivers may be three or more.

  In FIG. 21, each data driver DRa, DRb includes 30 (Q) driver cells arranged side by side along the direction D2. In FIG. 21, the number of pixels in the horizontal scanning direction of the display panel (when the data lines of the display panel are driven by sharing with a plurality of integrated circuit devices) It is assumed that HPN is used, the number of blocks of the data driver block (number of block divisions) is DBN, and the number of input image data input to the driver cell in one horizontal scanning period is IN. Note that IN is equal to the number of read times RN of the image data in one horizontal scanning period described with reference to FIG. In this case, the number Q of driver cells can be expressed as Q = HPN / (DBN × IN). In the case of FIG. 21, since HPN = 240, DBN = 4, and IN = 2, Q = 240 / (4 × 2) = 30.

  Further, it is assumed that the number of subpixels in the horizontal scanning direction of the display panel is HPNS, and the multiplexing number of multiplexers of each driver cell is NDM. Then, the number Q of driver cells arranged along the direction D2 can be expressed as Q = HPNS / (DBN × IN × NDM). In the case of FIG. 21, since HPNS = 240 × 3 = 720, DBN = 4, IN = 2, and NDM = 3, Q = 720 / (4 × 2 × 3) = 30. For example, when the number of multiplexing increases and NDM = 6, Q = 720 / (4 × 2 × 6) = 15.

  Further, when the width (pitch) in the D2 direction of the driver cell is WD and the width in the D2 direction of the peripheral circuit portion (buffer circuit, wiring region, etc.) included in the data driver block is WPCB, the first to Nth The width WB (maximum width) of the circuit blocks CB1 to CBN in the D2 direction can be expressed as Q × WD ≦ WB <(Q + 1) × WD + WPCB. Further, when the width in the D2 direction of the peripheral circuit portion (row address decoder RD, wiring area, etc.) included in the memory block is WPC, it can be expressed as Q × WD ≦ WB <(Q + 1) × WD + WPC.

  Further, the number of pixels in the horizontal scanning direction of the display panel is HPN, the number of bits of image data for one pixel is PDB, the number of memory blocks is MBN (= DBN), and data is read from the memory block in one horizontal scanning period. Assume that the number of times of reading image data is RN. In this case, the number P of sense amplifiers (sense amplifiers that output 1-bit image data) arranged in the direction D2 in the sense amplifier block SAB is expressed as P = (HPN × PDB) / (MBN × RN). be able to. In the case of FIG. 21, since HPN = 240, PDB = 24, MBN = 4, and RN = 2, P = (240 × 24) / (4 × 2) = 720. Note that the number P is the number of effective sense amplifiers corresponding to the number of effective memory cells, and does not include the number of ineffective sense amplifiers such as sense amplifiers for dummy memory cells.

  Further, it is assumed that the number of subpixels in the horizontal scanning direction of the display panel is HPNS, and the multiplexing number of multiplexers of each driver cell is NDM. Then, the number P of sense amplifiers arranged along the direction D2 can be expressed as P = (HPNS × PDB) / (MBN × RN × NDM). In the case of FIG. 21, since HPNS = 240 × 3 = 720, PDB = 24, MBN = 4, RN = 2, and NDM = 3, P = (720 × 24) / (4 × 2 × 3) = 720.

  When the width (pitch) in the D2 direction of each sense amplifier included in the sense amplifier block SAB is WS, the width WSAB in the D2 direction of the sense amplifier block SAB (memory block) is WSAB = P × WS. Can be represented. The width WB (maximum width) in the D2 direction of the circuit blocks CB1 to CBN is P × WS ≦ WB <(P + PDB) when the width in the D2 direction of the peripheral circuit portion included in the memory block is WPC. It can also be expressed as × WS + WPC.

13. Electronic Device FIGS. 22A and 22B show examples of an electronic device (electro-optical device) including the integrated circuit device 10 of this embodiment. Note that the electronic device may include components other than those illustrated in FIGS. 22A and 22B (for example, a camera, an operation unit, a power supply, or the like). The electronic device according to the present embodiment is not limited to a mobile phone, and may be a digital camera, a PDA, an electronic notebook, an electronic dictionary, a projector, a rear projection television, a portable information terminal, or the like.

  22A and 22B, the host device 410 is, for example, an MPU or a baseband engine. The host device 410 controls the integrated circuit device 10 that is a display driver. Alternatively, processing as an application engine or baseband engine, or processing as a graphic engine such as compression, decompression, or sizing can be performed. Further, the image processing controller 420 in FIG. 22B performs processing as a graphic engine such as compression, decompression, and sizing on behalf of the host device 410.

  In the case of FIG. 22A, an integrated circuit device 10 with a built-in memory can be used. That is, in this case, the integrated circuit device 10 once writes the image data from the host device 410 into the built-in memory, reads the written image data from the built-in memory, and drives the display panel. On the other hand, in the case of FIG. 22B, an integrated circuit device 10 without a memory can be used. That is, in this case, the image data from the host device 410 is written into the built-in memory of the image processing controller 420. The integrated circuit device 10 drives the display panel 400 under the control of the image processing controller 420.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or drawings, terms (output-side I / F region, input) described at least once together with different terms (first interface region, second interface region, electro-optical element, etc.) having a broader meaning or the same meaning The term “side I / F region, liquid crystal element, and the like” can be replaced with the different terms in any place in the specification and the drawings. In addition, the scanning output line wiring method described in FIGS. 1 to 5 and the common voltage line wiring method described in FIGS. 6A to 9C are arranged as described in FIGS. 12 to 14A. The present invention can be applied not only to an integrated circuit device having a configuration, but also to an integrated circuit device having another arrangement configuration, for example, an integrated circuit device having an arrangement configuration shown in FIG. Further, the scanning output line may be wired in an area other than the link controller in order to bypass the physical layer circuit.

6 is an arrangement configuration example of an integrated circuit device using the scanning output line wiring method according to the embodiment. 9 is an arrangement configuration example of an integrated circuit device of a comparative example. 3A and 3B show detailed arrangement configuration examples of the integrated circuit device. Other arrangement composition examples of this embodiment. Explanatory drawing of the shield method of a scanning output line. FIGS. 6A to 6C are explanatory diagrams of a display panel. FIG. 7A to FIG. 7C are explanatory diagrams of a wiring method for common voltage lines. 4 is a detailed layout example of an integrated circuit device. FIG. 9A to FIG. 9C are explanatory diagrams of a shield method for the common voltage line. 6 is a circuit configuration example of an integrated circuit device. 11A and 11B are configuration examples of a high-speed I / F circuit and a physical layer circuit. 4 is an example of an arrangement configuration of an integrated circuit device. FIGS. 13A and 13B are planar layout examples of the integrated circuit device. 14A and 14B are examples of cross-sectional views of the integrated circuit device. 2 is a configuration example of a gradation voltage generation circuit. FIG. 16A and FIG. 16B are explanatory diagrams of an arrangement method of the gradation voltage generation circuit block. 17A shows an example of a signal waveform such as an address signal, and FIG. 17B shows an example of a register map. Explanatory drawing of a global wiring method. 19A and 19B are explanatory diagrams of a block division method for a memory and a data driver. Explanatory drawing of the method of reading image data in multiple times in 1 horizontal scanning period. Data driver and driver cell arrangement example. 22A and 22B are structural examples of electronic devices.

Explanation of symbols

CB1 to CBN 1st to Nth circuit blocks, GB gradation voltage generation circuit block,
DB, DB1 to DBJ Data driver block, MB memory block,
LB logic circuit block, HB high-speed I / F circuit block, PHY physical layer circuit,
LKC link controller, SB, SB1, SB2 scan driver block,
PR, PR1, PR2 Scan driver pad placement area,
VCB common voltage generation circuit, VCL common voltage line,
10 integrated circuit device, 12 output side I / F area, 14 input side I / F area,
20 memory, 22 memory cell array, 24 row address decoder,
26 column address decoder, 28 write / read circuit,
40 logic circuit, 42 control circuit, 44 display timing control circuit,
46 host interface circuit, 48 RGB interface circuit,
50 data drivers, 70 scan drivers, 90 power supply circuits,
110 gradation voltage generation circuit, 120 ladder resistance circuit, 130 gradation voltage setting circuit,
140 control circuit, 142 gradation register unit, 144 address decoder,
200 High-speed I / F circuit, 210, 220 Physical layer circuit, 230 Link controller, 232 Packet analysis circuit, 234 Packet generation circuit, 240 Driver I / F circuit, 400 Display panel, 410 Host device, 420 Image processing controller

Claims (15)

At least one scan driver block for driving a scan line of the electro-optical device provided with the electro-optical element ;
A high-speed interface circuit block for transferring data via a serial bus using a differential signal;
A scan driver pad arrangement region in which pads for electrically connecting the scan output lines of the scan driver block and the scan lines are arranged;
The high-speed interface circuit block includes:
A physical layer circuit for receiving data using the differential signal;
A link controller that performs link layer processing,
A scan output line which is an output line of the scan driver block is wired on the link controller so as to bypass the physical layer circuit from the scan driver block to the scan driver pad arrangement region. Integrated circuit device. In claim 1,
The high-speed interface circuit block and the scan driver block are arranged along a first direction,
When the direction orthogonal to the first direction is the second direction, the scan driver pad arrangement region is provided on the second direction side of the high-speed interface circuit block and the scan driver block. An integrated circuit device. In claim 2,
The integrated circuit device, wherein the link controller is disposed on the second direction side of the physical layer circuit. In any one of Claims 1 thru | or 3,
A logic circuit block that receives the data received by the high-speed interface circuit block and controls the scan driver block;
The integrated circuit device, wherein the high-speed interface circuit block is disposed between the logic circuit block and the scan driver block. In claim 4,
An integrated circuit device, wherein the logic circuit block and the link controller are integrated and formed by automatic placement and wiring. In any one of Claims 1 thru | or 5,
In the link controller, a shield line is wired under a scan output line of the scan driver block passing over the link controller. In any one of Claims 1 thru | or 6.
At least one data driver block for driving data lines of the electro-optical device ;
A common voltage generation circuit for generating a common voltage applied to the counter electrode of the electro-optical device ;
First and second common voltage pads for outputting the common voltage generated by the common voltage generation circuit to the outside,
When the direction orthogonal to the first direction is the second direction, the opposite direction of the first direction is the third direction, and the opposite direction of the second direction is the fourth direction,
The first common voltage pad is disposed on the third direction side of the data driver block, and the second common voltage pad is disposed on the first direction side of the data driver block.
First and second differential input pads for inputting the first and second signals constituting the differential signal from the outside are disposed on the fourth direction side of the physical layer circuit,
A common voltage line connecting between the first and second common voltage pads is located on the fourth direction side of the data driver block from the first common voltage pad to the second common voltage pad. In the region, the wiring is routed along the first direction, and in the region on the third direction side of the physical layer circuit, the wiring is routed along the second direction, and the physical layer circuit is in the second direction. An integrated circuit device, wherein the integrated circuit device is wired along the first direction in a region on the side, and is wired along the fourth direction in a region on the first direction side of the physical layer circuit . In claim 7 ,
The integrated circuit device, wherein the common voltage line is wired along the first direction on the second direction side of the link controller. In claim 7 or 8 ,
An integrated circuit comprising: a first shield line formed of a wiring layer different from the common voltage line and provided with a given power supply potential so as to overlap the common voltage line apparatus. In any one of Claims 7 thru | or 9 ,
An integrated circuit device, wherein a second shield line formed of a wiring layer that is the same layer as the common voltage line and provided with a given power supply potential is wired on both sides of the common voltage line. In any one of Claims 1 thru | or 6 .
First to Nth circuit blocks (N is an integer of 3 or more) are arranged along the first direction,
At least one data driver block for driving data lines of the electro-optical device ;
A gradation voltage generation circuit block for generating a plurality of gradation voltages;
A logic circuit block that receives data received by the high-speed interface circuit block and transfers grayscale adjustment data for adjusting a grayscale voltage to the grayscale voltage generation circuit block ;
Provided as three of the first to Nth circuit blocks;
When the direction orthogonal to the first direction is the second direction, the opposite direction of the first direction is the third direction, and the opposite direction of the second direction is the fourth direction, The grayscale voltage generation circuit block is disposed on the third direction side of the data driver block, and the high-speed interface circuit block and the logic circuit block are disposed on the first direction side of the data driver block. An integrated circuit device. In claim 11 ,
Between adjacent circuit blocks of the first to Nth circuit blocks, the wiring below the I-th layer (I is an integer of 3 or more, indicating that the higher I is the higher layer ) Local lines formed with layers are wired,
Between non-adjacent circuit blocks among the first to Nth circuit blocks, a global line formed by a wiring layer of the I-th layer or higher is disposed on the circuit block interposed between non-adjacent circuit blocks. Wired along the direction of 1,
A gradation global line for supplying a gradation voltage from the gradation voltage generation circuit block to the data driver block is wired along the first direction on the data driver block. Integrated circuit device. In any one of Claims 1 thru | or 6 .
First to Nth circuit blocks (N is an integer of 3 or more) are arranged along the first direction,
At least one data driver block for driving data lines of the electro-optical device ;
A power supply circuit block for generating a power supply voltage;
A logic circuit block that receives data received by the high-speed interface circuit block and transfers power supply adjustment data for adjusting a power supply voltage to the power supply circuit block ;
Provided as three of the first to Nth circuit blocks;
When the direction orthogonal to the first direction is the second direction, the opposite direction of the first direction is the third direction, and the opposite direction of the second direction is the fourth direction, The power supply circuit block is disposed on the third direction side of the data driver block, and the high-speed interface circuit block and the logic circuit block are disposed on the first direction side of the data driver block. An integrated circuit device. In claim 13 ,
Between adjacent circuit blocks of the first to Nth circuit blocks, the wiring below the I-th layer (I is an integer of 3 or more, indicating that the higher I is the higher layer ) Local lines formed with layers are wired,
Between non-adjacent circuit blocks among the first to Nth circuit blocks, a global line formed by a wiring layer of the I-th layer or higher is disposed on the circuit block interposed between non-adjacent circuit blocks. Wired along the direction of 1,
An integrated circuit device, wherein a power global line for supplying a power supply voltage from the power supply circuit block to the data driver block is wired along the first direction on the data driver block. An integrated circuit device according to any one of claims 1 to 14 ,
The electro-optical device driven by the integrated circuit device;
An electronic device comprising:

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