KR950009919A - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

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Publication number
KR950009919A
KR950009919A KR1019930017450A KR930017450A KR950009919A KR 950009919 A KR950009919 A KR 950009919A KR 1019930017450 A KR1019930017450 A KR 1019930017450A KR 930017450 A KR930017450 A KR 930017450A KR 950009919 A KR950009919 A KR 950009919A
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KR
South Korea
Prior art keywords
layer
metal wiring
semiconductor device
forming
aluminum alloy
Prior art date
Application number
KR1019930017450A
Other languages
Korean (ko)
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KR960016227B1 (en
Inventor
김헌도
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR93017450A priority Critical patent/KR960016227B1/en
Publication of KR950009919A publication Critical patent/KR950009919A/en
Application granted granted Critical
Publication of KR960016227B1 publication Critical patent/KR960016227B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 금속배선 형성방법을 기술한 것으로, 실리콘 기판 또는 도전층에 콘택하는 평탄화된 금속배선을 형성할 때 하나의 알루미늄 증착챔버로 가열용 아르곤 개스의 유입을 조절함에 의해 알루미늄 합금의 증착온도를 조절하는 방법으로 저온 알루미늄 합금층을 증착한 후 고온 알루미늄 합금층을 증착하면서 평탄화하는 반도체 소자의 금속배선 형성방법이 기술된다.The present invention describes a method of forming a metal wiring of a semiconductor device, and when forming a planarized metal wiring contacting a silicon substrate or a conductive layer, the aluminum alloy is controlled by controlling the inflow of argon gas for heating to one aluminum deposition chamber. As a method of controlling the deposition temperature, a method of forming a metal wiring of a semiconductor device is disclosed, in which a low temperature aluminum alloy layer is deposited and then planarized by depositing a high temperature aluminum alloy layer.

Description

반도체 소자의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1a도 내지 제1c도는 본 발명에 의한 반도체 소자의 금속배선을 형성하는 단계를 도시한 단면도.1A to 1C are cross-sectional views showing steps of forming metal wirings of a semiconductor device according to the present invention.

Claims (1)

실리콘 기판 또는 도전층과 같은 콘택 기판(1) 상부에 절연층(2)을 형성한 후, 콘택 마스크를 사용하여 상기 절연층(2)의 소정부분에 콘택 홀(3)을 형성한 다음, 상기 콘택 홀(3) 및 절연층(2)의 상부에 배리어 금속층(4) 및 티타늄층(5)을 중착하고, 알루미늄 증착 챔버를 이용하여 알루미늄을 증착 및 평탄화하는 반도체 소자의 금속 배선 형성방법에 있어서, 상기 티타늄층(5)을 증착한 후 스퍼터링 장비에서 대기중에 노출됨이 없이 고온, 고진공으로 유지된 알루미늄 증착챔버로 이동시켜 웨이퍼 가열용 아르곤 개스를 유입하지 않은 50∼100℃의 저온상태에서 제1알루미늄 합금층(6a)을 증착한 후, 상기 알루미늄 증착챔버에 웨이퍼 가열용 아르곤 개스를 유입하여 온도를 증가시켜 400∼550℃의 고온상태가 되었을때 제2 알루미늄 합금층(6a)을 증착하면서 평탄화하여 제1 및 제2알루미늄 합금층(6a 및 6b)으로 평탄화된 금속배선(6)을 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.After the insulating layer 2 is formed on the contact substrate 1 such as a silicon substrate or a conductive layer, a contact hole 3 is formed in a predetermined portion of the insulating layer 2 by using a contact mask. In the method of forming a metal wiring of a semiconductor device in which the barrier metal layer 4 and the titanium layer 5 are deposited on the contact hole 3 and the insulating layer 2, and aluminum is deposited and planarized using an aluminum deposition chamber. After depositing the titanium layer 5, the sputtering equipment is moved to an aluminum deposition chamber maintained at a high temperature and high vacuum without being exposed to the atmosphere, and thus, the first layer is heated at a low temperature of 50 to 100 ° C. without introducing an argon gas for wafer heating. After depositing the aluminum alloy layer 6a, the argon gas for heating the wafer is introduced into the aluminum deposition chamber to increase the temperature to deposit the second aluminum alloy layer 6a when the temperature is 400 to 550 ° C. The first and second aluminum alloy layer (6a and 6b), a metal wiring method for forming a semiconductor device of the features forming the metal wiring 6 is planarized. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR93017450A 1993-09-02 1993-09-02 Semiconductor metal wire forming method KR960016227B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93017450A KR960016227B1 (en) 1993-09-02 1993-09-02 Semiconductor metal wire forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93017450A KR960016227B1 (en) 1993-09-02 1993-09-02 Semiconductor metal wire forming method

Publications (2)

Publication Number Publication Date
KR950009919A true KR950009919A (en) 1995-04-26
KR960016227B1 KR960016227B1 (en) 1996-12-07

Family

ID=19362685

Family Applications (1)

Application Number Title Priority Date Filing Date
KR93017450A KR960016227B1 (en) 1993-09-02 1993-09-02 Semiconductor metal wire forming method

Country Status (1)

Country Link
KR (1) KR960016227B1 (en)

Also Published As

Publication number Publication date
KR960016227B1 (en) 1996-12-07

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