KR950007959B1 - Metalization method of semiconductor device - Google Patents
Metalization method of semiconductor device Download PDFInfo
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- KR950007959B1 KR950007959B1 KR1019920010884A KR920010884A KR950007959B1 KR 950007959 B1 KR950007959 B1 KR 950007959B1 KR 1019920010884 A KR1019920010884 A KR 1019920010884A KR 920010884 A KR920010884 A KR 920010884A KR 950007959 B1 KR950007959 B1 KR 950007959B1
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
Description
제1도는 종래 반도체의 금속배선 형성공정도.1 is a process diagram for forming a metal wiring of a conventional semiconductor.
제2도는 본 발명에 따른 반도체의 금속배선 형성공정도.2 is a process diagram of forming a metal wiring of a semiconductor according to the present invention.
제3도는 본 발명에 따른 다른 실시예의 금속배선 형성공정도.3 is a metal wiring forming process diagram of another embodiment according to the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 실리콘기판 22 : 절연막21 silicon substrate 22 insulating film
23 : P+확산층 24 : 제1폴리실리콘23: P + diffusion layer 24: the first polysilicon
25 : 텅스텐 26 : 제2폴리실리콘25: tungsten 26: second polysilicon
27 : 베리어메탈 28 : 알루미늄27: barrier metal 28: aluminum
본 발명은 반도체의 금속배선 혀성방법에 관한 것으로서, 특히 미세한 콘택홀에 텅스텐플러그를 형성하고 P+콘택저항을 감소되도록 하여 고집적화에 적당하도록 한 반도체의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for guiding metal wiring of semiconductors, and more particularly, to a method for forming metal wiring of semiconductors, which is suitable for high integration by forming tungsten plugs in fine contact holes and reducing P + contact resistance.
일반적으로 널리 이용되고 있는 반도체의 금속배선공정은 제1도에 도시된 바와 같이 통상적인 방법에 의하여 트랜지스터를 형성한 다음 (a)도에서와 같이 금속배선이 놓여질 부분에 절연막(2)을 에치하여 콘택홀을 형성한 후 상기 콘택홀 아래의 실리콘기판(1)상에 콘택저항을 낮추기 위해 TiSi2(3)층을 형성한 다음 확산에 의해 TiN(4)을 절연막(2) 측벽과 실리콘기판(1)에 증착하고 이어서 스퍼터링으로 텅스텐(5)을 증착하여 베리어메탈층을 형성한다.In general, the metal wiring process of a semiconductor is widely used, as shown in FIG. 1, by forming a transistor by a conventional method, and then etching the insulating film 2 on the portion where the metal wiring is to be placed, as shown in (a). After forming the contact hole, a layer of TiSi 2 (3) is formed on the silicon substrate 1 below the contact hole, and then TiN 4 is formed by diffusion into the sidewall of the insulating film 2 and the silicon substrate ( 1) and then tungsten (5) by sputtering to form a barrier metal layer.
이러한 상태에서 (b)도와 같이 화학기상증착(CVD)방법을 사용하여 금속 배선으로 이용될 텅스텐(6)을 전면에 데포지션하여 평탄화시킨 후 (c)도에서와 같이 상기 턴스텐(6)을 에치백하여 텅스텐플러그를 형성한 다음 알루미늄(7)을 증착함으로써 배선공정을 완료하게 된다.In this state, by using the chemical vapor deposition (CVD) method as shown in (b), the tungsten (6) to be used for metal wiring is deposited on the front surface and flattened. By etching back to form a tungsten plug and then depositing aluminum (7) to complete the wiring process.
이러한 종래의 반도체 금속배선 형성방법은 콘택저항을 낮추기 위하여 TiSi2를 형성할 때 B+등의 불순물이 실리콘기판으로부터 결핍되므로 P+콘택의 콘택저항(접촉저항)이 증가한다.In the conventional method of forming a semiconductor metal wiring, when the TiSi 2 is formed to lower the contact resistance, impurities such as B + are deficient from the silicon substrate, thereby increasing the contact resistance (contact resistance) of the P + contact.
또한, 콘택의 사이드월 경사면이 86°이상이고, 사이드월이 바우드(Bowed) 경사면을 갖는 경우에 CVD로 증착된 텅스텐의 플러그 중심부에 키(Key Hole)이 발생하므로 텅스텐 에치백이 과도한 경우에는 텅스텐플러그 중심부에 공극이 커져서 이후 알루미늄을 증착하면 그 부분에서 알루미늄막의 단차피복성(Step Coverage)이 좋지않게 되어 반도체소자의 신뢰성이 저하되는 문제점이 발생하게 된다.In addition, when the sidewall slope of the contact is 86 ° or more and the sidewall has the Bowed slope, a key hole is generated in the plug center of the CVD-deposited tungsten. If the pores become larger in the center of the plug and subsequently aluminum is deposited, the step coverage of the aluminum film becomes poor at that portion, resulting in a problem that the reliability of the semiconductor device is degraded.
본 발명은 상기와 같은 문제점을 해결하기 위하여 콘택과 실리콘기판 사이에 기판과 같은 종류로 도핑된 폴리실리콘막을 형성하고, 블랭킷(Blanket) 텅스텐을 증착하여 W-P+실리콘의 콘택이 직접 형성됨에 따라 P+콘택저항을 감소되도록 하며, 또한 텅스텐 키홀을 제거하여 반도체의 신뢰성을 향상시키기 위한 것으로서, 본 발명의 목적은 반도체의 금속배선 형성방법에 있어서, 실리콘기판에 소스/드레인영역의 P+확산층을 형성한 다음 실리콘기판 위에 절연막을 데포지션한 후 사진식각공정으로 배선이 형성될 부분에 콘택홀을 형성하는 단계와, 상기 콘택홀을 형성한 후 제1폴리실리콘층을 형성하는 단계와, 텅스텐을 화학기상증착법에 의하여 증착하는 단계와, 상기 단계후 제2폴리실리콘을 증착하는 단계와, 상기 제2폴리실리콘층을 에치백하여 평탄화하는 단계와, 상기 제2폴리실리콘과 텡스텐을 동시에 에치백하여 플러그를 형성하는 단계를 포함하는 반도체의 금속배선 형성방법을 제공하는데 있다.In order to solve the above problems, the present invention forms a doped polysilicon layer between the contact and the silicon substrate as a kind of substrate, and deposits blanket tungsten to directly form the contact of W + P + silicon. In order to reduce the contact resistance and to improve the reliability of the semiconductor by removing the tungsten keyhole, an object of the present invention is to form a P + diffusion layer of the source / drain region on the silicon substrate in the method of forming a metal wiring of the semiconductor Depositing an insulating film on a silicon substrate and forming a contact hole in a portion where a wiring is to be formed by a photolithography process, forming a first polysilicon layer after forming the contact hole, and chemical vapor deposition of tungsten Depositing a second polysilicon layer and depositing a second polysilicon layer after the step; And forming a plug by simultaneously etching back the second polysilicon and tungsten to form a plug.
이하 첨부된 도면에 의해 상세히 설명하면 다음과 같다.Hereinafter, described in detail by the accompanying drawings as follows.
제2도는 본 발명에 따른 반도체의 금속배선 형성공정도로서, 먼저 (a)도에 도시된 바와같이 실리콘기판(21)에 소스와 드레인영역을 형성하여 P+확산층(23)을 형성한 다음 절연막(22)을 데포지션하고, 상기 절연막(22)을 에치하여 배선이 형성될 위치에 콘택홀을 형성한다.FIG. 2 is a process diagram of forming a metal wiring of a semiconductor according to the present invention. First, as shown in FIG. 1A, a source and a drain region are formed on a silicon substrate 21 to form a P + diffusion layer 23, and then an insulating film 22 ) And form a contact hole at the position where the wiring is to be formed by etching the insulating film 22.
상기 공정이 완료되면 (b)도와 같이 절연막(22)측벽과 P+확산층(23)에 제1폴리실리콘(24)을 2000Å 이하의 두께로 증착하여 콘택저항을 낮춘 다음 이후 증착될 텅스텐의 균일한 핵생성을 위하여 P도우핑영역(P+콘택을 포함하는 영역)이외의 부분에 감광막을 도포한 다음 Sb+ 또는 SF+, B+등의 이온을 주입한다.When the process is completed, as shown in (b), the first polysilicon 24 is deposited on the sidewall of the insulating film 22 and the P + diffusion layer 23 to a thickness of 2000 kΩ or less to lower the contact resistance, and then uniform nuclei of tungsten to be deposited. For production, a photosensitive film is applied to a portion other than the P doping region (the region including the P + contact), and then ions such as Sb + or SF +, B + are implanted.
상기 공정을 완료한 후 (c)도에서와 같이 텅스텐(25)을 H2환원 또는 SiH4환원 등을 이용하여 화학기상증착(CVD)방법으로 콘택홀의 반지름보다 얇은 두께로 증착하여 공극을 형성한 다음 상기 텅스텐(25)전면에 제2폴리실리콘(26)을 텅스텐(25)의 공극 반지름 이상의 두께로 증착하여 공극을 메운 다음 (d)도와같이 O2와 CF4가스를 포함하는 에칭가스를 이용하여 제2폴리실리콘(26)의 에치백을 실시함으로써 평탄화시킨다.After completing the above process, as shown in (c), tungsten (25) was deposited to a thickness thinner than the radius of the contact hole by chemical vapor deposition (CVD) using H 2 reduction or SiH 4 reduction to form voids. Next, the second polysilicon 26 is deposited on the entire surface of the tungsten 25 to a thickness greater than or equal to the pore radius of the tungsten 25 to fill the pores, and as shown in (d), an etching gas including O 2 and CF 4 gas is used. By flattening the second polysilicon 26 by etching.
상기 공정완료 후 (e)도에 도시된 바와같이, 제2폴리실리콘(26)과 텅스텐(25)을 식각선택비(제2폴리실리콘의 식각속도+텅스텐의 식각속도)가 0.5~1.5로 되도록 CF4, SF2또는 CF6의 혼합가스를 이용하여 상기 제2폴리실리콘(26)과 텅스텐(25) 및 제1폴리플러그(24)를 에치백하여 콘택플러그를 형성한다.After completion of the process, as shown in (e), the second polysilicon 26 and tungsten 25 have an etching selectivity (etch rate of the second polysilicon + etching rate of tungsten) to be 0.5 to 1.5. The second polysilicon 26, tungsten 25 and the first polyplug 24 are etched back using a mixed gas of CF 4 , SF 2 or CF 6 to form a contact plug.
그 다음(f)도와 같이 절연막(22)와 콘택플러그 전면에 Ti, TiN 또는 Ti/TiN을 증착하여 베리어메탈(27)을 형성하고, 상기 베리어메탈(27)위에 배선으로 사용될 알루미늄(28)을 데포지션한다.Next, as shown in (f), the barrier metal 27 is formed by depositing Ti, TiN, or Ti / TiN on the insulating film 22 and the contact plug front surface, and the aluminum 28 to be used as the wiring on the barrier metal 27 is formed. Deposition.
상기 공정 후 (g)도와 같이, 베리어메탈(27)과 알루미늄(28)을 에치하여 배선으로 쓰일 부분만 남기고 나머지를 제거함으로써 배선공정을 완료하게 된다.After the step (g), the barrier metal 27 and the aluminum 28 are etched away, leaving only the portion to be used as the wiring and removing the rest, thereby completing the wiring process.
제3도는 본 발명에 따른 금속배선공정의 다른 실시예를 도시한 것으로서, 반도체의 금속배선 형성방법에 있어서, 실리콘기판에 소스/드레인영역의 P+확산층을 형성한 다음 실리콘기판 위에 절연막을 데포지션한 후 사진 식각공정으로 배선이 형성될 부분에 콘택홀을 형성하는 단계와, 상기 콘택홀을 형성한 후 제1폴리실리콘층을 형성하는 단계와, 텅스텐을 화학기상증착법에 의하여 증착하는 단계와, 상기 단계 후 제2폴리실리콘을 증착하는 단계와, 상기 제2폴리실리콘층을 에치백하여 평탄화하는 단계와, 상기 제2폴리실리콘과 텅스텐만을 에치백하여 제1폴리실리콘이 잔류되도록 플러그를 형성하는 단계로 이루어지며 이후의 공정은 동일하다.3 shows another embodiment of the metallization process according to the present invention. In the method for forming metallization of a semiconductor, a P + diffusion layer of a source / drain region is formed on a silicon substrate and then an insulating film is deposited on the silicon substrate. Forming a contact hole in a portion where a wiring is to be formed by a photolithography process, forming a first polysilicon layer after forming the contact hole, depositing tungsten by chemical vapor deposition, and Depositing a second polysilicon after the step, etching the second polysilicon layer to planarize, and etching only the second polysilicon and tungsten to form a plug such that the first polysilicon remains. The process is the same.
즉, (a)도에 도시된 바와같이 실리콘기판(21)에 소스와 드레인영역을 형성하여 P+확산층 (23)을 형성한 다음 절연막(22)을 데포지션하고, 상기 절연막(21)을 에치하여 배선이 형성될 위치에 콘택홀을 형성한다.That is, as shown in (a), the source and drain regions are formed on the silicon substrate 21 to form the P + diffusion layer 23, and then the insulating film 22 is deposited and the insulating film 21 is etched. A contact hole is formed at the position where the wiring is to be formed.
상기 공정이 완료되면 (b)도와 같이 절연막(22) 측벽과 P+확산층(23)에 제1폴리실리콘(24)을 2000Å 이하의 두께로 증착하여 콘택저항을 낮춘 다음 이후 증착될 텅스텐의 균일한 핵생성을 위하여 P도우핑영역(P+콘택을 포함하는 영역)이외의 부분에 감광막을 도포한 다음 Sb+ 또는 BF+, B+등의 이온을 주입한다.When the process is completed, as shown in (b), the first polysilicon 24 is deposited on the sidewall of the insulating film 22 and the P + diffusion layer 23 to a thickness of 2000 GPa or less to lower the contact resistance, and then uniform nuclei of tungsten to be deposited. For production, a photosensitive film is applied to a portion other than the P doping region (the region including the P + contact), and then ions such as Sb +, BF +, and B + are implanted.
상기 공정을 완료한 후 (c)도에서와 같이 텅스텐(25)을 H2환원 또는 SiH4환원 등을 이용하여 화학기상증착(CVD) 방법으로 콘택홀의 반지름보다 얇은 두께로 증착하여 공극을 형성한 다음 상기 텅스텐(25)전면에 제2폴리실리콘(26)을 텅스텐(25)의 공극 반지름 이상의 두께로 증착하여 공극을 메운 다음 (d)도와 같이 O2와 CF4가스를 포함하는 에칭가스를 이용하여 제2폴리실리콘(26)을 에치백 실시함으로써 평탄화시킨다.After completing the above process, as shown in (c), tungsten (25) was deposited to a thickness thinner than the radius of the contact hole by chemical vapor deposition (CVD) using H 2 reduction or SiH 4 reduction to form voids. Next, the second polysilicon 26 is deposited on the entire surface of the tungsten 25 to a thickness greater than or equal to the pore radius of the tungsten 25 to fill the pores, and as shown in (d), an etching gas containing O 2 and CF 4 gas is used. To be flattened by etching back the second polysilicon 26.
상기 공정완료후 (e)도에 도시된 바와같이 텅스텐(25)과 제2폴리실리콘(26)을 부분적으로 에치백하여 절연막(22) 위에 제1폴리실리콘(1)이 잔류되도록 한 상태에서 콘택플러그를 형성하도록 한다.After the completion of the process, as shown in (e), the tungsten 25 and the second polysilicon 26 are partially etched back so that the first polysilicon 1 remains on the insulating film 22. Make a plug.
그 다음 (f)에서와 같이 콘택플러그와 제1폴리실리콘(24)위에 Ti, TiN 또는 Ti/TiN을 증착하여 베리어메탈(27)을 형성하고, 상기 베리어메탈(27)위에 배선으로 사용될 알루미늄(28)을 데포지션한다.Then, as in (f), Ti, TiN, or Ti / TiN is deposited on the contact plug and the first polysilicon 24 to form a barrier metal 27, and the aluminum to be used as a wiring on the barrier metal 27 ( Deposition 28).
상기 공정 후 (g)도와 같이, 베리어메탈(27)과 알루미늄(28)을 에치하여 배선으로 쓰일 부분만 남기고 나머지를 제거함으로써 배선공정을 완료하게 된다.After the step (g), the barrier metal 27 and the aluminum 28 are etched away, leaving only the portion to be used as the wiring and removing the rest, thereby completing the wiring process.
이상에서 상술한 바와 같이 본 발명은 CVD 방법으로 증착된 텅스텐의 핵생성을 위한 제1폴리실리콘층을 형성하고, 텅스텐을 콘택홀의 반지름보다 얇은 두께로 증착한 후 형성된 공극부분을 다시 제2폴리실리콘으로 증착하여 제거한 후 제2폴리실리콘을 에치백하여 평탄화하고, 제1폴리실리콘과 텅스텐을 식각선택비가 0.5~1.5로 되도록 식각가스 조성을 조절하여 동시에 식각함으로써 플러그의 표면이 평탄하게 되도록하고 또한 n+ 및 P+확산층과의 콘택저항을 낮추기 위하여 텅스텐 핵생성을 위한 제2폴리실리콘층을 별도의 감광막 마스크를 이용하여 이온주입함으로써 텅스텐 P+실리콘의 콘택이 직접 형성되므로 기존의 텅스텐 Ti-Si2-P+ 실리콘인 경우와 같이 도펀트(Dopant)의 실리콘기판에서 결핍이 일어나지 않게 되어 P+콘택저항이 감소할 뿐만 아니라 텅스텐 키홀을 제거하고, 폴리실리콘에 의하여 대체할 수 있는 효과를 제공하게 되는 것이다.As described above, the present invention forms a first polysilicon layer for nucleation of tungsten deposited by the CVD method, and deposits tungsten to a thickness thinner than the radius of the contact hole, thereby forming the second polysilicon again. After evaporation and removal, the second polysilicon is etched back to be flattened, and the first polysilicon and tungsten are etched to adjust the etching gas composition so that the etching selectivity is 0.5 to 1.5. In order to reduce the contact resistance with the P + diffusion layer, a tungsten P + silicon contact is directly formed by ion implanting a second polysilicon layer for tungsten nucleation using a separate photoresist mask so that the conventional tungsten Ti-Si 2 -P + silicon As is the case, dopants do not occur in the silicon substrate of the dopant, which not only reduces P + contact resistance, Removing the stent keyhole, and which will provide an effect that can be replaced by a polysilicon.
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| KR100351456B1 (en) * | 1999-12-31 | 2002-09-09 | 주식회사 하이닉스반도체 | Method for fabricating an SRAM device |
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