KR930004111B1 - Forming method of metal wire in semiconductor device - Google Patents

Forming method of metal wire in semiconductor device Download PDF

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KR930004111B1
KR930004111B1 KR1019900010611A KR900010611A KR930004111B1 KR 930004111 B1 KR930004111 B1 KR 930004111B1 KR 1019900010611 A KR1019900010611 A KR 1019900010611A KR 900010611 A KR900010611 A KR 900010611A KR 930004111 B1 KR930004111 B1 KR 930004111B1
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substrate
film
forming
depositing
plug
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KR1019900010611A
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Korean (ko)
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KR920003418A (en
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전영권
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

The metal wiring is formed by (a) forming an insulating film (1) on the silicon substrate (9), and then etching it to form a contact, (b) depositing a barrier metal (2), (c) first-depositing an amorphous silicon film (3) for a plug on the whole surface of the substrate, and then ion-implanting impurities, (d) second- depositing the amorphous silicon film on the whole surface of the substrate, and then etch-backing it by the dry-etching to form an amorphous silicon plug (3'), (e) depositing a titanium film (4) on the substrate, (f) forming a titanium nitride (5) on the film (4), and forming a titanium silicide on the contact by heat- treating the substrate on the nitrogen atmosphere, and (g) forming a metal wiring (7) on the substrate.

Description

금속배선 형성방법Metal wiring formation method

제1(a)도-제1(c)도는 종래의 금속배선 형성 공정도.1 (a) to 1 (c) are conventional metal wiring forming process diagrams.

제2(a)도-제2(e)도는 본 발명에 따른 금속배선 형성 공정도.2 (a) to 2 (e) is a process diagram for forming a metal wiring according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 절연막 2 : 배리어금속1 insulating film 2 barrier metal

3 : 다결정 실리콘 4 : 티타늄막3: polycrystalline silicon 4: titanium film

5 : 질화티타늄막 6 : 티타늄 실리사이드5: titanium nitride film 6: titanium silicide

7 : 배선금속 8 : 비활성층7: wiring metal 8: inactive layer

본 발명은 반도체 집적회로의 금속배선 형성방법에 관한 것으로, 특히 콘택홀(Contact hole)이나 비어홀(Via Hole)에 티타늄 실리사이드막(TiSi2)으로 플러그(Plug)를 형성한 후 금속배선을 형성하여 줌으로써 금속배선의 평탄화 및 접촉저항을 감소시킬 수 있도록 한 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring in a semiconductor integrated circuit. In particular, a metal wiring is formed after a plug is formed of a titanium silicide layer (TiSi 2 ) in a contact hole or a via hole. The present invention relates to a method for forming a metal wiring to reduce planarization and contact resistance of the metal wiring.

일반적으로 반도체 집적회로의 집적도가 높아짐에 따라 콘택부의 지름에 대한 높이의 비(Aspect Ratio)가 커지게 되며, 콘택홀의 크기가 작아짐에 따라 통상의 스퍼터링(Sputtering) 공정으로는 콘택홀(Contact Hole) 내부까지 금속원자가 도달할 확률이 낮아지므로 금속배선의 단차 피복성(Step Coverage)이 악화된다.In general, as the degree of integration of semiconductor integrated circuits increases, an aspect ratio of the diameter of the contact portion increases, and as the size of the contact hole decreases, a contact sputtering process is used as a normal sputtering process. Since the probability of reaching the metal atoms to the inside becomes low, the step coverage of the metal wiring is deteriorated.

따라서, 이와 같은 단점을 극복하기 위하여 종래에는 텅스텐(W)이나 다결정 실리콘(Si) 플로그를 콘택홀에 형성한 후 금속배선을 하여줌으로써 금속배선의 단차 피복성을 좋게 하려고 시도하였으나, 텅스텐은 그의 화학증착 반응의 연구가 진행되고 있어 개발 단계에 불과한 문제점이 있었다.Therefore, in order to overcome such drawbacks, conventionally, tungsten (W) or polycrystalline silicon (Si) plugs are formed in contact holes, and metal wiring is performed to improve the step coverage of the metal wiring. As the deposition reaction is being studied, there is only a problem in the development stage.

종래의 다결정 실리콘 플러그를 이용하여 금속배선을 형성하는 방법을 설명하면 다음과 같다.Referring to the method of forming a metal wiring by using a conventional polycrystalline silicon plug as follows.

제1(a)도에 도시된 바와 같이 실리콘기판(9)에 절연막(1)을 형성한 후 식각하여 콘택을 형성하고, 제1(b)도에 도시된 바와 같이 다결정 실리콘(3)을 증착한후 건식식각하여 다결정 실리콘 플러그(3')를 형성한다.As shown in FIG. 1 (a), an insulating film 1 is formed on the silicon substrate 9, followed by etching to form a contact, and as shown in FIG. 1 (b), polycrystalline silicon 3 is deposited. After dry etching, a polycrystalline silicon plug 3 'is formed.

제1(c)도에 도시된 바와 같이 기판전면에 걸쳐 배리어 금속(Barrier Metal)(2)을 증착한 후 배선금속(7)을 형성한다.As shown in FIG. 1 (c), the barrier metal 2 is deposited over the entire surface of the substrate, and then the wiring metal 7 is formed.

그러나 상기한 바와 같은 방법으로 금속배선을 형성하는 경우에는 다결정 실리콘의 접촉 저항이 높고 표면 거칠기(Surface Roughness)가 큰 결점이 있다.However, in the case of forming the metal wiring by the method described above, polycrystalline silicon has a high contact resistance and a large surface roughness.

본 발명은 상기한 바와 같은 종래 기술의 문제점을 해결하기 위한 것으로서, 콘택부위에 종래의 다결정 실리콘 플러그 대신에 저접촉저항을 갖는 티타늄 실리사이드를 형성하여 평탄화시킨 후 금속배선을 형성함으로써 접촉저항을 감소시키고 금속배선의 단차 피복성을 향상시킬 수 있는 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art as described above, instead of the conventional polycrystalline silicon plug to form a planarized titanium silicide having a low contact resistance after forming a metal wiring to reduce the contact resistance It is an object of the present invention to provide a method for forming a metal wiring that can improve the step coverage of the metal wiring.

이하 본 발명의 실시예를 첨부도면에 의거하여 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제2(a)도에 도시된 바와 같이 실리콘기판(9)상에 절연막(1)을 형성한 후 식각하여 콘택을 형성하고, 기판전면에 걸쳐 배리어 금속(2)을 증착한다.As shown in FIG. 2 (a), an insulating film 1 is formed on the silicon substrate 9 and then etched to form a contact, and the barrier metal 2 is deposited over the entire surface of the substrate.

제2(b)도에 도시된 바와 같이 비정질 실리콘(혹은 다결정 실리콘)(3)을 2,000Å 이하의 두께로 증착하고, 저저항 및 실리사이드(silicide) 반응 스톱(Stop)을 위한 불순물 이온을 주입한다.As shown in FIG. 2 (b), amorphous silicon (or polycrystalline silicon) 3 is deposited to a thickness of 2,000 μs or less, and implanted with impurity ions for low resistance and silicide reaction stop. .

이후 제2(c)도에 도시된 바와 같이 재차 비정질 실리콘(혹은 다결정 실리콘)(3)을 증착하고, 건식식각법으로 에치 백(etch back)하여 다결정 실리콘 플러그(3')를 형성한다.Thereafter, as shown in FIG. 2 (c), amorphous silicon (or polycrystalline silicon) 3 is again deposited and etched back by dry etching to form a polycrystalline silicon plug 3 '.

이어서 티타늄(Ti)막(4)을 콘택 깊이의 1/2 이하의 두께로 기판전면에 걸쳐 증착한다.Subsequently, a titanium (Ti) film 4 is deposited over the entire surface of the substrate to a thickness of 1/2 or less of the contact depth.

제2(d)도에 도시된 바와 같이 질소분위기에서 열처리하여 티타늄막(4)의 표면에는 질화티타늄막(5)을 형성시키고, 콘택에는 티타늄 실리사이드(6)가 형성된다. 이어서 배선금속(7)을 형성한다.As shown in FIG. 2 (d), a titanium nitride film 5 is formed on the surface of the titanium film 4 by heat treatment in a nitrogen atmosphere, and titanium silicide 6 is formed on the contact. Subsequently, the wiring metal 7 is formed.

제2(b)도에서의 이온주입공정에 의해 다결정 실리콘 플러그(3)까지만 티타늄 실리사이드(6)로 반응하고 실리콘기판(9)이 티타늄 실리사이드로 되는 것은 방지된다. 이는 도우핑되지 않은 다결정 실리콘막 보다 도우핑된 다결정 실리콘막이 반응속도가 느려 도우핑된 다결정 실리콘막에서 실리사이드 반응이 멈추기 때문이다.By the ion implantation process in FIG. 2 (b), only up to the polycrystalline silicon plug 3 is reacted with titanium silicide 6, and the silicon substrate 9 is prevented from becoming titanium silicide. This is because the silicide reaction is stopped in the doped polycrystalline silicon film because the doped polycrystalline silicon film is slower than the undoped polycrystalline silicon film.

제2(e)도는 본 발명의 금속배선 형성방법에 따라 평탄화된 저저항 전극 배선을 형성하여 제작한 반도체 소자의 단면도를 도시한 것으로서, 미 설명부호 8은 비활성층(Passivation layer)이다.FIG. 2E shows a cross-sectional view of a semiconductor device fabricated by forming flattened low resistance electrode wirings according to the metallization forming method of the present invention. Reference numeral 8 denotes a passivation layer.

따라서 상기한 바와 같은 본 발명에 따르면, 종래의 콘택에 다결정 실리콘 플러그를 형성하는 방법 대신에 저저항을 갖는 티타늄 실리사이드 플러그를 형성하여 줌으로써 콘택에서의 접촉저항을 감소시킬 수 있으며, 콘택에 플러그를 형성하여 평탄화한 후 금속배선을 형성함으로써 금속배선의 단차 피복성을 향상시킬 수 있는 효과를 갖는다.Therefore, according to the present invention as described above, by forming a titanium silicide plug having a low resistance instead of a method of forming a polycrystalline silicon plug in a conventional contact, it is possible to reduce the contact resistance in the contact, forming a plug in the contact By forming the metal wiring after planarization, the step coverage of the metal wiring can be improved.

Claims (2)

실리콘기판(9)상에 절연막(1)을 형성한 후 식각하여 콘택을 형성하는 단계와, 배리어 금속(2)을 증착하는 단계와, 플러그용 비정질 실리콘막(3)을 1차로 기판전면에 증착한 후 불순물 이온주입하는 단계와, 플러그용 비정질 실리콘막을 2차로 기판전면에 증착한 후 건식식각법으로 에치백하여 비정질 실리콘 플러그(3')를 형성하는 단계와, 티타늄막(4)을 증착하는 단계와, 질소분위기에서 열처리하여 티타늄막(4)의 표면상에는 질화티타늄막(5)이 형성되고 콘택에서는 비정질 실리콘 플러그(3')를 티타늄 실리사이드(6)로 형성하는 단계와, 기판전면에 배선금속(7)을 형성하는 단계를 포함하는 것을 특징으로 하는 금속배선 형성방법.Forming an insulating film 1 on the silicon substrate 9 and then etching to form a contact; depositing a barrier metal 2; depositing a plug amorphous silicon film 3 on the front surface of the substrate. And then implanting impurity ions, depositing the amorphous silicon film for the plug secondly on the entire surface of the substrate, and then etching back by dry etching to form the amorphous silicon plug 3 ', and depositing the titanium film 4. And a heat treatment in a nitrogen atmosphere to form a titanium nitride film 5 on the surface of the titanium film 4, and to form an amorphous silicon plug 3 'with titanium silicide 6 at the contact, and to wire the substrate. Forming a metal (7). 제1항에 있어서, 플러그용 비정질 실리콘막(3) 대신 다결정 실리콘막을 사용하는 것을 특징으로 하는 금속배선 형성방법.2. The method of forming a metal wiring according to claim 1, wherein a polycrystalline silicon film is used instead of the plugged amorphous silicon film (3).
KR1019900010611A 1990-07-13 1990-07-13 Forming method of metal wire in semiconductor device KR930004111B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100851438B1 (en) * 2007-02-05 2008-08-11 주식회사 테라세미콘 Method for fabricating semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100851438B1 (en) * 2007-02-05 2008-08-11 주식회사 테라세미콘 Method for fabricating semiconductor device

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