KR950007108A - Capacitor Manufacturing Method - Google Patents

Capacitor Manufacturing Method Download PDF

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Publication number
KR950007108A
KR950007108A KR1019930016049A KR930016049A KR950007108A KR 950007108 A KR950007108 A KR 950007108A KR 1019930016049 A KR1019930016049 A KR 1019930016049A KR 930016049 A KR930016049 A KR 930016049A KR 950007108 A KR950007108 A KR 950007108A
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KR
South Korea
Prior art keywords
gate electrode
capacitor
spacer
insulating film
film
Prior art date
Application number
KR1019930016049A
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Korean (ko)
Other versions
KR100251983B1 (en
Inventor
박상훈
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930016049A priority Critical patent/KR100251983B1/en
Publication of KR950007108A publication Critical patent/KR950007108A/en
Application granted granted Critical
Publication of KR100251983B1 publication Critical patent/KR100251983B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체 소자의 제조공정중 캐패시터 형성방법에 관한 것으로, 특히 자기정렬된 포켓 이온주입에 의한 게이트전극 형성후 남게되는 잔류 스페이서를 유효 캐패시터로 사용하는 캐패시터 제조방법에 관한 것으로써 게이트전극을 형성하기 위한 감광막 패턴을 이용하여 저온공정에 의한 산화막스페이서를 형성하고 감광막을 차단막으로 하여 리액티브이온에칭(Reactive Ion Etching) 방법으로 자기 정렬된 게이트전극 측벽홀을 간단히 형성할 수 있고, 또한 이때 잔류하는 산화막스페이서를 캐패시터로 이용할 수 있게 하여 캐패시턴스를 증대시킨 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor during a manufacturing process of a semiconductor device, and more particularly, to a method of manufacturing a capacitor using a residual spacer left after the formation of a gate electrode by self-aligned pocket ion implantation as an effective capacitor. By using a photosensitive film pattern to form an oxide spacer by a low temperature process, the gate electrode sidewall holes self-aligned by a reactive ion etching method using a photosensitive film as a blocking film can be simply formed, The capacitance can be increased by allowing the oxide spacer to be used as a capacitor.

Description

캐패시터 제조방법Capacitor Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 일 실시예에 따른 캐패시터 제조 공정단면도.2 is a cross-sectional view of a capacitor manufacturing process according to an embodiment of the present invention.

Claims (4)

반도체 소자의 제조공정중 캐패시터의 형성방법에 있어서, 실리콘기판(1)에 필드산화막(20), 게이트산화막(2), 폴리실리콘막을 형성한 다음, 감광막(6)을 차단막으로 상기 폴리실리콘막, 게이트산화막(2)을 식각하여 게이트전극(3)을 형성하되 상기 게이트전극(3) 상부의 감광막(6)은 남긴 후 상기 식각으로 드러난 실리콘기판에 제1불순물을 이온주입하는 단계와, 상기 감광막(6) 및 게이트전극(3) 측벽에 절연막스페이서(7)을 형성하고 제2불순물을 이온주입하는 단계와, 전체구조 상부에 평탄화용 감광막(26)을 도포하는 단계와, 상기 평탄화용 감광막(26)을 에치백하여 상기 절연막스페이서(7)의 상단이 드러나도록 하는 단계와, 상기 게이트적극(3) 측벽부위의 절연막스페이서(7)를 소정크기 식각하여 제거한 다음, 노출된 실리콘기판(1)에 제3불순물을 이온주입하는 단계를 포함하여 이루어지는 것을 특징으로 하는 캐패시터 제조방법.In the method of forming a capacitor during the manufacturing process of a semiconductor device, a field oxide film 20, a gate oxide film 2, and a polysilicon film are formed on a silicon substrate 1, and then the polysilicon film, Etching the gate oxide film 2 to form a gate electrode 3, leaving a photoresist film 6 on the gate electrode 3, and ion implanting a first impurity into the silicon substrate exposed by the etching; (6) and forming an insulating film spacer (7) on the sidewalls of the gate electrode (3) and ion implanting a second impurity, applying a planarizing photosensitive film (26) over the entire structure, and the planarizing photosensitive film ( 26 to etch back to expose the upper end of the insulating film spacer 7 and to remove the insulating film spacer 7 on the sidewall portion of the gate electrode 3 by a predetermined size, and then to expose the exposed silicon substrate 1. Ion wine with the third impurity in Step capacitor manufacturing method comprising the a. 제1항에 있어서, 상기 절연막스페이서(7)는 450℃이하의 저온공정에 의해 형성되는 것을 특징으로 하는 캐패시터 제조방법.The method of manufacturing a capacitor according to claim 1, wherein the insulating film spacer (7) is formed by a low temperature process of 450 deg. 제1항에 있어서, 상기 절연막스페이서(7)는 리액티브이온에칭(Reactive Ion Etching; RIE)방법으로 식각하는 것을 특징으로 하는 캐패시터 제조방법.The method of claim 1, wherein the insulating film spacer (7) is etched by reactive ion etching (RIE). 제1항 또는 제2항에 있어서, 상기 절연막스페이서(7)는 산화막으로 형성된 산화막스페이서인 것을 특징으로 하는 캐패시터 제조방법.A method according to claim 1 or 2, characterized in that the insulating film spacer (7) is an oxide film spacer formed of an oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930016049A 1993-08-18 1993-08-18 The fabricating method of capacitor KR100251983B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930016049A KR100251983B1 (en) 1993-08-18 1993-08-18 The fabricating method of capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930016049A KR100251983B1 (en) 1993-08-18 1993-08-18 The fabricating method of capacitor

Publications (2)

Publication Number Publication Date
KR950007108A true KR950007108A (en) 1995-03-21
KR100251983B1 KR100251983B1 (en) 2000-04-15

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KR1019930016049A KR100251983B1 (en) 1993-08-18 1993-08-18 The fabricating method of capacitor

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