KR950004741A - Parallel buffer system on the system control module board - Google Patents
Parallel buffer system on the system control module board Download PDFInfo
- Publication number
- KR950004741A KR950004741A KR1019930014026A KR930014026A KR950004741A KR 950004741 A KR950004741 A KR 950004741A KR 1019930014026 A KR1019930014026 A KR 1019930014026A KR 930014026 A KR930014026 A KR 930014026A KR 950004741 A KR950004741 A KR 950004741A
- Authority
- KR
- South Korea
- Prior art keywords
- buffer
- data
- control module
- module board
- control signal
- Prior art date
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Abstract
본 발명의 목적은 병렬버퍼의 이용 및 버퍼램의 중재시기를 조정하여 버퍼램의 사용권을 가지고 있는 사이클 수를 줄이도록 하는 시스템 제어 모듈 보드의 병령버퍼 시스템에 관한 것으로 이와 같은 본 발명은 DMA 제어수단의 제1제어신호에 따라 시스템 버스를 통한 데이타를 일시저장 및 입력되는 데이타 시스템 버스로 송출하는 제1 데이타 버퍼와, 상기 DMA 제어수단의 제2 제어 신호에 따라 제 1데이타 버퍼를 통한 데이타를 각각 저장 후 이 각각 저장된 데이타를 버퍼램에 순차 저장시킴과 아울러 버퍼램에 저장된 데이타를 순차 저장하는 제2내지 제 5데이타 버퍼를 구성함으로써 달성되어 지는 것이다.SUMMARY OF THE INVENTION The present invention relates to a parallel buffer system of a system control module board for adjusting the use of a parallel buffer and the arbitration timing of a buffer RAM to reduce the number of cycles for which the buffer RAM is licensed. A first data buffer for temporarily storing and transmitting data through the system bus according to a first control signal of the first data buffer and data through a first data buffer according to a second control signal of the DMA control means. This is achieved by constructing a second to fifth data buffer which sequentially stores the data stored in the buffer RAM after storing the data stored in the buffer RAM sequentially.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제 3 도는 본 발명 시스템 제어모듈 보드의 병렬버퍼 시스템 블럭구성도, 제 4 도의 (가)는 제 3 도의 각부상태를 보인도이고, (나)는 (가)의 서브상태를 보인도이다.3 is a block diagram of a parallel buffer system of the system control module board of the present invention. FIG. 4A is a diagram showing the parts of FIG. 3, and FIG. 4B is a diagram showing a substate of FIG.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930014026A KR950004741A (en) | 1993-07-23 | 1993-07-23 | Parallel buffer system on the system control module board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930014026A KR950004741A (en) | 1993-07-23 | 1993-07-23 | Parallel buffer system on the system control module board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR950004741A true KR950004741A (en) | 1995-02-18 |
Family
ID=67142910
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930014026A KR950004741A (en) | 1993-07-23 | 1993-07-23 | Parallel buffer system on the system control module board |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR950004741A (en) |
-
1993
- 1993-07-23 KR KR1019930014026A patent/KR950004741A/en not_active Application Discontinuation
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |