KR950004577A - Method and apparatus for forming bipolar and MOS devices on the same substrate - Google Patents

Abstract

The present invention relates to a process and an apparatus for simultaneously forming a bipolar device and a MOS device on the same semiconductor substrate. Separating the bipolar region, which is a first region, and the MOS region, which is a second region, formed on the silicon substrate, and forming an oxide layer and a polysilicon layer thereon; Implanting impurities into the gate electrode forming portions of the first region and the second region opened by the photolithography method to form active and exogenous base regions and high concentration channel regions; Forming a high concentration collector region under the base region by implanting impurities of the same conductivity type as the first region into an emitter connection region joined to the active base region of the first region opened by a photolithography method; Forming a conductive layer over the substrate and forming an emitter region and a gate electrode pattern; Forming a source and a drain region by opening the second region to inject impurities therein; Forming a high concentration of exogenous base region by opening the first region and implanting impurities, which includes forming a BiCMOS semiconductor device using the present process.

Description

Method and apparatus for forming bipolar and MOS devices on the same substrate

Since this is an open matter, no full text was included.

2 (a) to (h) are process steps for manufacturing the semiconductor device of the present invention, and FIGS. 3 (a) and (b) are process charts for manufacturing a BiCMOS device according to the process of the present invention, FIG. (a) to (c) is a manufacturing process diagram of a BiCMOS device according to another embodiment of the present invention

Claims (10)

Separating the bipolar region, the first region, and the MOS region, the second region, formed on the silicon substrate, and forming an oxide layer and a polysilicon layer thereon; Implanting impurities into the gate electrode forming portions of the first region and the second region opened by the photolithography method to form active and exogenous base regions and high concentration channel regions; Forming a high concentration collector region under the base region by implanting impurities of the same conductivity type as the first region into an emitter connection region bonded to the active base region of the first region opened by a photolithography method; Forming a conductive layer over the substrate and forming an emitter region and a gate electrode pattern; Forming a source and a drain region by opening the second region to inject impurities therein; Forming a high concentration of exogenous base region by opening the first region and injecting impurities to form bipolar and MOS devices on the same substrate. The method of claim 1, further comprising forming gate sidewalls of the MOS device and sidewall spacers of the bipolar emitter after the source and drain regions of the second region are formed. And forming a high concentration source and drain region by implanting a high concentration impurity into the LDD-type MOS device, wherein the bipolar and MOS devices are formed on the same substrate. The method of claim 1, wherein the bipolar and MOS devices are formed on the same substrate, wherein the conductive layer for patterning the emitter region and the gate electrode is a polysilicon layer doped. Separating the bipolar region and the N-MOS and P-MOS regions formed on the silicon substrate and forming an oxide layer and a polysilicon layer thereon; Forming a base region and a highly concentrated channel region by implanting impurities of the same conductivity type as the N (P) MOS region in the gate electrode forming portions of the bipolar region and the N (P) MOS region opened by the photolithography method; Forming a high concentration collector region under the base region by implanting impurities of the same conductivity type as the region into an emitter connection region which is joined to the base region of the bipolar region opened by a photolithography method; Patterning a conductive layer formed over the entire surface of the substrate to form an emitter region, an N (P) MOS and a P (N) MOS gate electrode; Forming a source and a drain region by opening an N (P) mos region to implant impurities; A method of forming a BiCMOS semiconductor device, comprising forming a high concentration of an exogenous base region and a source and drain region of a P (N) mos by opening a bipolar region and a P (N) mos region to inject impurities. 5. The method of claim 4, further comprising opening a gate electrode forming region of a P (N) mos forming region to form a high concentration channel region when forming the high concentration collector region. 5. The method of claim 4, further comprising forming gate sidewalls of the MOS device and sidewall spacers of the bipolar emitter after formation of the source and drain regions of the N (P) MOS region, and N after formation of the exogenous base region. (P) A method of forming a BiCMOS semiconductor device, further comprising forming a high concentration source and a drain region by implanting a high concentration impurity into the moss region. The method of claim 4, wherein the conductive layer for patterning the emitter region and the gate electrode is a doped polysilicon layer. The method of manufacturing a BiCMOS semiconductor device according to claim 4, wherein the MOS element formation region of the same conductivity type as the region formed by the bipolar element is a wall region formed in the silicon substrate. In a semiconductor device having a bipolar element and a MOS element included in the same substrate, the baripolar element includes a base having an active base region and an exogenous base region, a collector having a high concentration impurity region in contact with the active base region, and the active base. And a patterned emitter in contact with a region, wherein the MOS device comprises a gate insulating layer, a gate electrode, a source / drain electrode, and a high concentration channel region. 10. The bipolar and MOS transistor apparatus according to claim 9, wherein the emitter and the gate electrode have insulating spacers on sidewalls thereof, and the MOS element is an LDD type MOS element. ※ Note: The disclosure is based on the initial application.