KR950004477A - Test Method of Semiconductor Wafers - Google Patents

Abstract

The method of testing semiconductor wafers improves test efficiency for all test lots. This method includes a first step and a second step. In the first step, the portion of the chip formed on the wafer is tested for all test items. In a second step, the remaining chips of the chips are tested for at least one test item of the selected test item based on the test result of the first step. The first and second steps are repeated for every wafer in the test lot.

Description

Test Method of Semiconductor Wafers

Since this is an open matter, no full text was included.

FIG. 3A is a flowchart for showing a process sequence of the method for testing a semiconductor wafer according to the first embodiment of the present invention, and FIG. 3B is a plan view of the semiconductor wafer for showing the method of the first embodiment shown in FIG. 3A.

Claims (6)

A test method for a semiconductor wafer comprising a plurality of chips for a given test item, comprising: performing a first test for testing some of the plurality of chips for all the given test items; Finding a test item from the given test items to test a remaining chip of the plurality of chips based on a result of the first test; And performing a second test on the test items found from the given test items to test the remaining chips of the plurality of chips. The method of claim 1, wherein the test item found from the given test items is a test item indicating that at least one of the chips is defective. N, L, and P are each integers greater than 1, L is greater than P, and in the number of L chips, P is tested for all N test items and for testing a semiconductor wafer containing L chips for N test items. A method comprising: (a) clearing first to Nth data in each first to Nth data register and setting the test chip number TT as 1 in the chip count register; (b) comparing the test chip number TT with the chip number P and setting the first data in the first register when the test chip number TT is greater than the chip number P; (c) testing a first chip for the first test item when the test chip number TT is not greater than the chip number P; (d) checking a test result of the first chip with respect to the first test item, and checking the first data in the first register only when the test result of the first chip of the first test item is not passed. Setting a; (e) testing the first chip for a second test item; (f) repeating the checking of step (d) and the testing of the third to Nth test items; (g) increasing the number of test chips by one; (h) comparing the increased number of test chips TT and the number of chips P; (i) checking the first data in the first data register after the first chip to the Pth chip is tested, and checking the first test item only when the first data is set in the first data register. Testing the (P + 1) th chip for; And (j) continuously checking the second data to the N-th data in the second data register to the N-th data register, and wherein the second data to the N-th data are respectively stored in the second data register to the N-th data register. And continuously testing the (P + 1) th chip for the second to Nth test items only when set. CLAIMS 1. A method of testing a semiconductor wafer comprising a plurality of chips for a given test item, the method comprising: (a) selecting one of the wafers; (b) performing a first test to test some of the plurality of chips of the selected wafer of the wafer for all the given test items; (c) finding a test item from the given test items for testing a remaining chip of the plurality of chips of the selected wafer of the wafer based on a result of the first test; (d) performing a second test on the test item found from the given test items to test a remaining chip of the plurality of chips of the selected one of the wafers; And (e) repeating steps (a), (b), (c) and (d) for the remaining wafers of the wafer. The method of claim 4, wherein the test item found from the given test items is a test item indicating that at least one of the chips is defective. N, L, and P are each integers greater than 1, L is greater than P, and in the number of L chips, P is tested for all N test items, and for each N test item is tested a semiconductor wafer containing L chips A method, comprising: a first step of selecting one of the wafers; And a second step of testing the selected one of the wafers, wherein the second step comprises: (a) clearing the first data to Nth data in each of the first data to Nth data registers; Setting the test chip number TT as 1 in the step 1; (b) comparing the test chip number TT with the chip number P and setting the first data in the first register when the test chip number TT is greater than the chip number P; (c) testing a first chip for the first test item when the test chip number TT is not greater than the chip number P; (d) checking a test result of the first chip with respect to the first test item, and checking the first data in the first register only when the test result of the first chip of the first test item is not passed. Setting a; (e) testing the first chip for a second test item; (f) repeating the checking of step (d) and the testing of the third to Nth test items; (g) increasing the number of test chips by one; (h) comparing the increased number of test chips TT and the number of chips P; (i) checking the first data in the first data register after the first chip to the Pth chip is tested, and checking the first test item only when the first data is set in the first data register. Testing the (P + 1) th chip for; And (j) continuously checking the second data to the N-th data in the second data register to the N-th data register, and wherein the second data to the N-th data are respectively stored in the second data register to the N-th data register. And continuously testing the (P + 1) th chip for the second to Nth test items only when set. ※ Note: The disclosure is based on the initial application.