JP2806748B2 - Wafer inspection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a semiconductor integrated circuit device, and more particularly, to a method for inspecting a wafer.

[0002]

2. Description of the Related Art In conventional wafer inspection, all chips are inspected for a predetermined number of wafers in a test lot composed of a plurality of wafers, and the above inspection is performed for most of the remaining wafers. From the results, a chip to be inspected was selected according to the position where the chip was arranged. For example, as shown in FIG. 4, inspection is performed on all chips for the first to Mth wafers in a test lot including X wafers, and thereafter, M + 1
For the wafers from the first wafer to the X-th wafer, the inspection is performed only for the chip located at the same position as the chip having a defective result in the inspection of the preceding M wafers. For some chips, inspection was omitted to improve the inspection efficiency of wafer lots.

Further, when there are a plurality of inspection items for inspecting all the chips of a predetermined number of wafers, inspection items for which all the chips of the remaining most number of wafers have no defect in the above inspection result. Was omitted, and only the remaining inspection items were inspected. For example, as shown in FIG. 5, for the first to Mth wafers in a test lot including X wafers, all chips are inspected for all inspection items, and then M + 1
For all the chips of the wafers from the first wafer to the Xth wafer, the inspection items which were good in all the chips in the previous inspection of the M wafers were omitted, and a result of failure was obtained in at least some of the chips. Only the remaining inspection items were inspected.

[0004]

In the above-described conventional wafer inspection method, several wafers in a wafer lot are inspected for all the chips, and from the result, the chips or the wafers to be inspected for most of the remaining wafers are inspected. By selecting test items and performing inspections, the aim was to improve the test efficiency of the entire wafer lot. Therefore, if the number of wafers per wafer lot is not sufficiently large, the expected effect cannot be obtained, such as lowering the inspection efficiency by performing the entire inspection on the first few wafers. In particular, the number of wafers required for a custom device such as an ASIC is small due to an increase in the number of chips in one wafer due to an increase in the wafer size.
A problem arises when the number of wafers to be tested is not large.

An object of the present invention is to shift the inspection target from a wafer lot to individual wafers, and to improve the inspection efficiency of each individual wafer rather than the test efficiency of the entire wafer lot. It is an object of the present invention to provide a method of inspecting a wafer that improves the wafer quality.

[0006]

According to a first aspect of the present invention, there is provided a method of inspecting a wafer having a plurality of chips, wherein a predetermined inspection item is inspected for a part of chips on one wafer . Yes and inspection process, the remaining chips on the wafer a second inspection step to inspect only test item selected by the examination results of the inspection process
You.

[0007]

The inspection of all the inspection items is performed for a predetermined number of the chips on one wafer, and the inspection items to be performed for most of the remaining chips are selected based on the inspection result.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1A is a flowchart showing a processing procedure of an embodiment of a wafer inspection method (test method) according to the present invention. FIG. 1B is a schematic diagram showing a test state of a chip on a wafer. Here, as shown in FIG. 1B, the number L of chips in the wafer is 20, and the predetermined number P of chips to be tested for all test items is 8. Note that the number of chips to be tested for all test items and the arrangement position can be arbitrarily selected. Also, (1), (2),
(3) and (4) indicate registers for storing the results of the four items of tests, and 1 is set when the test results are defective.
TT is a test chip number. SQ is a sequence number indicating a step in the flow.

In FIG. 1, TT = 1 is first set at SQ1, and the registers (1) to (4) are cleared.
Next, in SQ2, the chip number TT is compared with a predetermined chip number P. At this time, since TT (= 1) <P (= 8), S
Proceed to Q3, start testing the first chip, test 1
Execute Here, as shown in Table 1 showing the test items and the test results for a predetermined number of chips, for the chip of chip number 1, the test 1 passed, the test 2 failed, the test 3 passed, and the test 4 passed. In the test 1, a pass (good) is confirmed (SQ4), 1 is not set in the register (1) (SQ5), the process directly proceeds to SQ6, and the test 2 is executed. 1 is set (SQ7, S
Q8). Next, the process proceeds to SQ9 and SQ10 to execute test 3, the path is confirmed, and SQ11 stores 1 in the register (3).
Is not set. Next, test 4 is executed in the same manner (SQ
12, SQ13, SQ14), all tests are executed for the first chip, the chip number is incremented (SQ15), and the process proceeds to the test for the second chip. Similarly, SQ2 to SQ15 are executed up to the eighth chip.

Thus, the inspection process for all the inspection items up to the predetermined number P of chips is completed. According to the test results so far shown in Table 1, three chips failed in the functional test of test 1 and four chips failed in the input / output leak test of test 2.
The results of the test of the input / output level of the test 3 and the test of the delay time of the test 4 are passed for all the chips. Therefore, in the second inspection process to be performed next on the chips of chip numbers 9 to 20, the inspection items of the test 3 and the test 4 are omitted, and the test of only the inspection items of the test 1 and the test 2 is performed.

[0012]

[Table 1] That is, when proceeding to the ninth chip, first register (1)
It is checked whether or not 1 is set in Test No. 1. Since 1 is set, Test 1 is executed (SQ17, SQ1).
8) Then, check the register (2) and perform test 2 in the same manner.
(SQ19, SQ20). Next, when checking the register (3), it is 0, so test 3
Is omitted (SQ21), and the process proceeds to the register (4).
Since the register (4) is also kept at 0, the test 4 is omitted (SQ23), the test of the ninth chip is completed, and
Proceed to the test of the th chip. In the same manner, the test up to the twentieth chip is executed only for test 1 and test 2.

As described above, up to the predetermined number of chips 8, all four items are tested, and the ninth to the last 20 are tested.
Until the second chip, only two tests are performed. Therefore, the number of tests in the case of the conventional test method: 20 × 4 = 8
Compared to 0, the number of tests in the case of the method of the embodiment: 8 × 4 + 1
2 × 2 = 66, which is a substantial time reduction of about 18%.

Next, an embodiment of an inspection method for a plurality of wafers will be described.

FIG. 2A is a flowchart showing a processing procedure in the above embodiment. FIG. 2B shows FIG.
FIG. 4A is a flowchart of a test for each wafer in FIG. 4A, and is exactly the same as the flowchart of FIG. FIG. 3 is a schematic diagram showing a test state of a chip on each wafer. Here, the number of wafers is X, the number of chips in the wafer is L, and the predetermined number of chips to be tested for all inspection items is P. Further, the number of test items is N, the test chip number is TT, and (1), (2).
(N) indicates a register for storing test results for each test item.

First, before testing the first wafer, each register is initialized and the chip number is set to 1. That is, (1) = 0, (2) = 0,... (N) = 0, and TT = 1 (step 101). Then, the test of the first wafer is started (Step 102), and as shown in FIG. 2B (similar to FIG.
All the test items are tested, and thereafter, from the (P + 1) th chip to the Lth chip, the test is performed by omitting the test items in which no failure has occurred in the test for all the test items from the predetermined Pth chip. . When the test of the first wafer is completed, each register is initialized again, and the chip number is set to 2 (step 103).
Proceeding to the test of the second wafer (step 104), the test is repeated in the same manner. Then, the test is repeated until step 202 in which the test of the X wafers is completed.

As described above, the selection of the test item according to the characteristic variation in each wafer is repeated for each wafer, and the test time can be reduced without deteriorating the test quality.

[0018]

As described above, according to the present invention, the inspection items of the remaining chips that have not been tested are determined based on the inspection results obtained by performing the inspection of all the items for a predetermined number of chips for each wafer. The selection has an effect that the test time can be reduced for each wafer and the inspection of the wafer can be performed efficiently.

[Brief description of the drawings]

FIG. 1A is a flowchart showing a processing procedure of an embodiment of a wafer inspection method according to the present invention. (B) is FIG.
FIG. 7 is a schematic diagram showing a test state of a chip on a wafer in the embodiment shown in FIG.

FIG. 2A is a flowchart showing a processing procedure in one embodiment of the present inspection method for a plurality of wafers. FIG. 2B is a flowchart illustrating a test processing procedure for each wafer in FIG.

FIG. 3 is a schematic diagram showing a test state of a chip on a wafer in the embodiment shown in FIG. 2;

FIG. 4 is a schematic diagram showing a test situation of a chip for each wafer in a conventional wafer inspection method.

FIG. 5 is a schematic diagram showing a test state of a chip for each wafer in another conventional wafer inspection method.

[Explanation of symbols]

SQ sequence number TT chip number (1), (2) ... (N) Register for storing test results P predetermined number of chips L number of chips in wafer N test item number X number of wafers in wafer lot M predetermined number of wafers

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-44949 (JP, A) JP-A-4-71247 (JP, A) JP-A-60-226132 (JP, A) JP-A-59-1987 211874 (JP, A) JP-A-64-3640 (JP, A) JP-A-1-313845 (JP, A) JP-A-59-3337 (JP, A)

Claims (1)

(57) [Claims] 1. A method for inspecting a wafer having a plurality of chips, comprising: a first inspection step of inspecting a predetermined inspection item for a part of chips on one wafer; inspection method of a wafer, characterized in Rukoto that having a second inspection step to inspect only test item selected by the examination results of the inspection step for the remaining chips.