JPH05107322A - Failure analizing device and analizing method for integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a failure analysis method for an integrated circuit capable of specifying a failure location in a short time. CONSTITUTION:In a failure analysis method, a failure analysis is executed by changing the observation palce of an EB potential contrast image while storing layout used for manufacturing an LSI mask in the computer of an EB tester, outputting the data on a CRT and using a monitor figure as navigation. A point irradiation place on wiring in an observation area is decided by means of wiring layout data, and after difference between good and bad point irradiation information is taken, the failure information is superimposed on a wiring image.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly to a failure analysis method for a logic integrated circuit.

[0002]

2. Description of the Related Art The number of integrated circuits of integrated circuits (hereinafter referred to as LSI) has been increasing year by year, and now logic integrated circuits having hundreds of thousands of gates have been introduced. Failure analysis of an LSI having such millions of transistors is extremely difficult even with the wisdom of the designer himself, and it is not uncommon for a failure location to be identified for only one month. Furthermore, it is almost impossible for anyone other than the designer to perform failure analysis. However, since the LSI user himself / herself can analyze the ASIC and the device designer can make a mask pattern by CAD processing after the functional design and logic design of the LSI for the ASIC, the designer cannot know the mask layout at all. Is occurring. Further ASI
In the factory for exclusive use of C and the factory for exclusive use of microcomputer, when the yield is improved by using these LSIs, the production engineers are gradually increasing the number of phases of analysis for the improvement of the yield. In order to meet such demands, there have been methods such as incorporating an internal test circuit to find the location of failure as easily as possible.However, since the chip size is large and it is not versatile, it is necessary to test. There were problems such as the number of man-hours involved in circuit design.

On the other hand, T. May 1984 Reliability Physics Conference with “Dyn
Amic Fault Imaging of VLS
The technique called DFI (Dynamic Fault Imaging), which was announced under the heading of "I Random Logic Devices", attracted much attention because it solves many of the problems described above. When the driving LSI chip is irradiated with an electron beam (hereinafter referred to as EB), secondary electrons come out from the surface, and when the wiring is at a high potential, most of the ejected electrons are pulled back and thus electrons are emitted. The number of electrons that reach the detector is small, while many electrons are detected when the potential is low, so that a contrast image can be obtained by the potential of the wiring. An electron beam tester (hereinafter, EB tester) that applies this principle 2 is used to find a defective portion by the method shown in Fig. 2. The vertical axis represents the position of the LSI chip. The horizontal axis is the time axis and the LSI test patterns (test vectors) are input from the input terminals one after another, so it may be considered in the order of test pattern numbers. The potential contrast image of each test pattern is dynamically captured, the potential contrast image of the defective product is captured, and the difference image is obtained to obtain a failure image. This is a case where the information of "1" and "0" appearing on the bonding pad is different from the expected value.By tracing the failure image while returning the test pattern number to the smaller number, the failure location is logically generated. The location can be found, and the cause of failure can be found by physically analyzing the location.

By using this method, it is possible to find a defective portion even if there is no design layout data or if this LSI designer is not the designer.

Normally, acquisition and editing of DFI images (defective product image, non-defective product image, failure image) are performed on a workstation. Conventionally, when narrowing down the failure point by the DFI method, the position information on the chip is used for the CRT of the workstation.
As a means to be taken on the screen, layout design information as CAD information or SEM image information is used.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the FI method, the beam is applied to the entire area in the visual field at a certain magnification. For this reason, for example, when sweeping the beam up to a magnification at which the potential image of the wiring can be clearly distinguished,
It takes a very long time to finish sweeping all the chips. For example, if the chip is 10mm square, 400μ
Sweeping the beam in angular size requires 625 sweeps. When it is determined that the tester is defective in the 3000th pattern, the potential image is captured while rotating the test pattern from 0 to 3000 many times, so that it takes several minutes to several tens of minutes in the 400 μ square size. It takes several days to repeat this process for each pattern and to find a defective portion by performing good products and defective products. Therefore, it is almost impossible to capture the electric potential image for all the combinations in terms of location and time. Therefore, there is proposed a method of interactively narrowing down the failure portion while tracing the failure image locally instead of the automatic determination method. However, as described above, when tracing is performed at a magnification at which the wiring is clearly visible, there is no means for knowing which position of the chip the observation region at that time is, and the failure image is often lost. In addition, the conventional EB sweep method has a drawback that it takes a long time.

When the position information is obtained by the layout design information as CAD information or the information of the SEM image, there are the following problems. (1) Layout design data as CAD information This information is usually difficult for the user side of the integrated circuit. Even if this information is available to the user of the integrated circuit, both soft and hard interface equipment cannot be prepared easily. (2) Information of SEM information Since this information is mainly the contrast reflecting the shape of the surface, it is difficult to obtain the positional information of the wiring or diffusion layer other than the uppermost layer.

An object of the present invention is to provide a method for narrowing down a failure portion of a semiconductor integrated circuit, which solves the above problems.

[0009]

The first gist of the present invention is to provide an electron beam generator for irradiating an integrated circuit device including a plurality of wirings having different depths from the surface with an electron beam, and an electron beam generator for irradiating the electron beam. A failure analysis device for an integrated circuit device, comprising: a detector for detecting a secondary electron beam generated in the integrated circuit device; and a position control means for controlling an irradiation position of an electric beam on the integrated circuit device. The difference in the depth from the surface of the plurality of wirings is determined based on the difference in the intensity, and the wiring pattern indicating the difference in the depth from the surface is displayed on the monitor screen based on the determination result.

A second aspect of the present invention is, in a failure analysis method for an integrated circuit device including a plurality of wirings having different depths from the surface, a step of irradiating the plurality of wirings with an electron beam and a surface of the wirings. And a step of forming a potential contrast image based on the intensity distribution of the secondary electron beam according to the difference in the depth from, and a step of forming layout data based on the potential contrast image and displaying the layout data as a monitor screen.

To solve the first problem, the potential contrast image of the EB tester described above is used to extract the image of the wiring and temporarily store the data on the entire surface of the chip to create the wiring layout data, which is used for navigation. It can be solved by using it as a tool. The wiring can be either high potential or low potential and therefore can be extracted from the initial test pattern.

The latter problem is to determine the spot irradiation location on the wiring in the observation area from the above wiring layout data, determine the difference between the good and defective spot irradiation information, and then use this difference information in the wiring image. This can be solved by adopting a method of superimposing. In this method, the so-called field area other than the wiring area does not need to be irradiated with the beam, and the irradiation is performed not on the entire surface of the wiring area but on point irradiation, so that the irradiation time is reduced from several hundredths to several thousandths of the conventional time. can do.

Further, in the failure analysis method of the present invention, the irradiation points of the electron beam are arranged in a two-dimensional lattice. By setting this grid interval equal to, for example, the wire interval of the integrated circuit and aligning the central portions of some wires with the grid points, the potential of each wire can be selectively obtained. This selectivity is several hundredth of that in the case of capturing a potential contrast image by the conventional DFI. This is because the point information that is conventionally used for the surface information is aggregated into the lattice points. The time required to obtain information can be shortened by the selection rate, that is, several hundred times.

Further, the point information for each of the good product and the defective product can be obtained by performing the method of preparing the lattice points and fitting the lattice points to the integrated circuit. By comparing the point information and the corresponding one-to-one correspondence, it is possible to find a point where the potential is different between the corresponding point information between the good product and the defective product. It can be pointed out where on the integrated circuit there is a defect depending on the order of the point in the information sequence. In this case, it is possible to eliminate the misalignment of the alignment of the potential contrast image and the ambiguity of the defective product determination due to the nonuniformity of the wiring widths of the good product and the defective product, which are problems in the conventional DFI. It will be possible.

[0015]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a diagram showing a first embodiment of a failure analysis apparatus of the present invention. This failure analysis device includes a lens barrel 101 of an EB tester, an EB generator 102, a test board 104, and an X board.
Y stage 105, secondary electron detector 106, LSI 10
LSI tester 1 which gives power supply voltage and test pattern to 3
07, the XY stage drive device 108, the beam pulse control device 110, the detected secondary electrons are processed into image information, this information is accumulated, and the EB irradiation position is calculated from the image data to obtain the beam pulse control device 110. And a CPU 109 for controlling the XY stage driving device 108, and a CRT 111 for displaying the obtained layout monitor diagram and potential contrast image.

Next, the analysis procedure performed by this failure analysis apparatus will be described with reference to the flow chart of FIG.

First, the LSI 103 is connected to the test board 104.
It is placed on top (S1) and a potential contrast image of the LSI is obtained (S2). At this time, any test pattern may be used. Therefore, the potential information is extracted while rotating the first pattern. At this time, regardless of the high and low electric potentials of the wirings, all that appears as an image is captured as a wiring image (S3).

FIGS. 4 to 6 are examples for better understanding of the wiring image obtained from this device. The logic circuit shown by FIG. 4 is implemented by the mask layout diagram of FIG. FIG. 6 is a potential contrast image of this portion. 1
The A1 wiring of the second layer and the A1 wiring pattern of the second layer are extracted.
Here, the polysilicon wiring potential contrast image is not displayed. H (high potential) and L (low potential) shown in FIG.
According to the above logic, the black portion 31 is H (high potential) and the white portion 32 is L (low potential). In this example, the thickness of the first layer A1 and the second layer A1 are not different, but in reality, the amount of electrons reaching the electron detector 106 is different because the thickness of the insulating film on the wiring is different. Is also different. By utilizing this, the first layer Al and the second layer Al can be distinguished.

FIG. 7 is a sectional view of this LSI, in which 401 is a silicon substrate, 402 is a diffusion layer, and 40 is a diffusion layer.
3 is a polysilicon wiring layer, 404 is a first layer Al, 405
Is a second layer Al, and 406 is an insulating film. Reference numerals 1, 2, 3 and 1 ', 2', 3'represent the incident EB and the emitted secondary electron beam, respectively.

FIG. 8 shows the emitted electron beam 1 ',
2 ', 3'intensity distributions are shown. As can be seen from the figure, the secondary electrons emitted from the insulating film 406 are affected by the electric field of each underlying wiring. Insulating film 4 on each layer
Since the type and thickness of 06 are different, the way of being affected by the same high potential is as shown in FIG. By setting a threshold value for each layer, it is possible to distinguish from which layer the electron beam originates. Therefore, at least for the wiring layers, the first layer aluminum wiring 404 and the second layer aluminum wiring 405, and further polysilicon are used. A layout diagram of the wiring 403 can be created. As described above, even if data is captured at a high magnification, it is not necessary to rotate a long pattern, and after capturing, only the image processing time of the CPU is required, and a wiring layout image can be obtained in a short time. FIG. 9 shows a screen on the CRT 80. In the multi-window mode, the entire navigation monitor diagram 82 obtained by the above method is displayed on the right, and the potential contrast image 81 of the place currently investigated is displayed on the left. By highlighting the current location on the monitor diagram 82, failure analysis becomes easier. Of course, the magnification of the monitor screen 82 for the right navigation can be returned freely.

Next, the shortening of the beam sweep time will be described. After obtaining the layout diagram again in FIG. 3, the wiring data is divided into some rectangles (S4). Figure 10
(A)-(c) is a figure for demonstrating how to divide | segment a rectangle. First layer aluminum wiring 91 and second layer aluminum wiring 92
Let's use the example where are crossing each other. In this field of view, the aluminum wiring 92 of the second layer is recognized as shown in FIG.
Since this layer has the same potential, it is not necessary to sweep the beam along all the surfaces as indicated by the dotted line 93 in FIG. 10A, and it is sufficient to obtain potential information of at least one point. The beam irradiation location is indicated by. On the other hand, FIG. 10C shows a beam irradiation place (• mark) of the first-layer aluminum wiring 91.
The irradiation place can be automatically or manually selected so as to avoid the overlapping portion of the first-layer aluminum wiring 91 and the second-layer aluminum wiring 92. The point coordinates indicating the irradiation position in the selected rectangle are registered (S5).

In the above description, the case where the first-layer aluminum wiring 91 and the second-layer aluminum wiring 92 can be completely distinguished has been described. However, even if each layer cannot be distinguished due to the problem of S / N ratio or resolution. , FIG. 10 (b '),
As shown in (c '), the sweep time can be greatly shortened by irradiating the beam at at least one place in the portion surrounded by the boundary line where the layers intersect.

Although the case where the shape is rectangular has been described above, there is essentially no problem even if the shape is a curve. It is only necessary to avoid an intersecting place or to incorporate an algorithm for selecting an arbitrary point in the CPU 109 of this embodiment. Irradiation at the registered EB irradiation coordinates is performed for non-defective products and defective products (FIG. 3, S6 and S7), and the difference is calculated (S8). After that, by copying this difference information onto a wiring layout image having a width (S9), a potential contrast image, that is, a failure image can be obtained.

In the flow of FIG. 3, the difference in the point information is taken first, but it is also possible to superimpose the point information on the layout image and then take this difference.

In the above, the method of registering the irradiation place is used in advance. However, it may be registered after the field of view at a place with a certain magnification is decided, for example, after the left screen of FIG. 9 is decided. On this occasion,
The layout monitor information can also be linked with this.

When obtaining the layout diagram, it is possible to make it together with information such as the diffusion layer previously captured by the optical microscope.

In the description of this embodiment, a non-defective product and a defective product are compared, that is, two LSIs are used. However, for example, at the stage of designing the cause of a timing defect or a power supply margin defective product, that is, one LSI. It is also possible to investigate which circuit block or which element caused this defect by comparing with.

Further, although the case where the potential contrast image is used has been described above, the potential information can be obtained by using the stroboscopic waveform obtained by the EB tester.

As described above, in this embodiment, the wiring image is extracted by using the potential contrast image or the waveform of the EB tester, and the stored wiring image is used as a navigation monitor. It facilitates the location trace of the failure analysis used.

Further, by only extracting from the above-mentioned wiring layout information only the wiring for which the potential information should be obtained from the EB whole surface irradiation, and changing the wiring to the point irradiation instead of the surface irradiation, the irradiation time can be greatly reduced. You can This makes it possible to automatically obtain a failure image for all patterns on the entire surface of the chip.

Next, a second embodiment of the present invention will be described with reference to the drawings.

11 to 16 are for explaining the present embodiment. FIG. 11 is a logic circuit diagram, and FIG. 12 is a mask layout diagram for realizing this. It is a two-layer Al process product. A P-channel transistor and an N-channel transistor are formed between the GND wiring 21 and the VCC wiring 22. Consider the logic indicated by H (high potential) and L (low potential) in FIG. The potential contrast image extracted by the EB tester is as shown in FIG. That is, the H portion 31 becomes black and the L portion becomes white. Conventionally, a method of irradiating EB over the front surface of this visual field has been adopted. However, it is not necessary to irradiate the area without wiring with EB. Therefore, in the present invention, the potential of the wiring is observed at at least one point.

14 and 15 show the first layer and the second layer, respectively.
It is a layout diagram of aluminum wiring of the layer. An appropriate position 41 as indicated by (.) Is automatically or manually designated from this mask data, and EB is irradiated only to this position. According to the conventional method, irradiation of 500 × 500 points was performed, but with the method of the present invention, 7 points are sufficient. Of course the first layer A
l is below the second layer Al, and the first layer A at this intersection
EB irradiation to 1 is impossible.

In the above example, even if the layers are connected to each other, the potential is observed twice, that is, even though the layers have the same potential, but in FIG. 16, the irradiation place is further reduced. There is. The connection relation between the layers is stored from the mask data registered in advance. For example, the second layer aluminum wiring 101 is electrically connected to the first layer aluminum wiring 102 and the polysilicon wiring 103. The second layer aluminum wiring 105 has the same potential as the first layer aluminum wiring 106.
Therefore, it suffices to irradiate one point of the most observable layer with EB. In this example, the four points 61 shown by (•) are used.
Will be enough. However, in this case, it cannot be applied to an LSI whose failure is expected to be a current leak failure, a disconnection failure, or the like.

FIG. 17 is a flow chart for explaining an example of the DFI failure analysis method using the above method. First, the place to be observed is placed in the field of view (S1). Next, the irradiation location is determined from the data of each layer of the design mask layout pattern of the field of view (S2). At this place, EB is irradiated onto the non-defective product to extract the potential (S3). The same is done for defective products (S4), and the difference between them is taken (S5). It means that the failure information of each layer is captured in points. A failure image can be obtained by copying this information into a layout pattern and processing it as a potential contrast image (S6). At this time, for example, when the potential difference between the good product and the defective product of the first layer aluminum wiring is (H)-(L), for example, red, (L)-
In the case of (H), the blue and second layer aluminum wirings are subjected to data processing in which a different color is applied to each, so that the failure image can be displayed more easily.

FIG. 18 illustrates how to display on the CRT 80 when the failure location is driven in using the DFI. An enlarged potential contrast image 81 of the currently observed place is shown on the left screen, and an entire image of the mask design pattern 82 is shown on the right screen. In this manner, the observation screen and the mask pattern are displayed in a multi-window to navigate the failure location while navigating, or by making them have the same magnification, the failure location can be more easily identified by superimposing them.

FIG. 19 shows points (hereinafter referred to as measurement points) for irradiating an electron beam arranged in a grid pattern, which shows the third embodiment of the present invention. The grid spacing is equal to the average spacing of the integrated circuit wiring being measured. The small circle 10 indicates the measurement point, and the numerical value attached to the upper right of the measurement point gives the rank to the small circle. FIG. 20 shows a state in which the measurement point group of FIG. 19 is applied to the integrated circuit. When a grid-like measurement point group is applied to the non-defective integrated circuit and the defective integrated circuit of FIG. 21 as shown in FIG. 20, a potential is obtained corresponding to each measurement point.
A potential contrast image for a good integrated circuit and a bad integrated circuit can be obtained. The hatched portion 11 shows a high level, and the white portion 12 shows a low level.

[0039]

[Table 1]

Table 1 shows the results of the electric potentials obtained at the respective measurement points. In the table, H indicates the high level of the potential of the integrated circuit, L indicates the low level, and I indicates the intermediate level. Where there is a difference, ◯ indicates that there is no difference, and x indicates that there is a difference. It can be seen from Table 1 that there is a mismatch between the potentials of the non-defective product and the defective product at the ninth measurement point. Figure 1
When 9 and FIG. 20 are combined, it is easy to see where the 9th measurement point is on the integrated circuit. Therefore, there is a mismatch point between a good product and a defective product, that is, a point where a logical failure occurs. It can be pointed out, and failure analysis can be done easily.

For the same purpose, as in the case of the conventional DFI, the potential contrast images of the non-defective product and the defective product were respectively taken, and they were superposed and the difference was found to find the mismatch. It took 100 times longer than taking the potential from the series. In addition, it was difficult to match the images, and there was ambiguity in determining the difference. In this way, in this embodiment, 100
It has been shown that failure analysis can be performed twice as fast and accurately.

In this embodiment, the lattice spacing is made equal to the average spacing of the wiring, but if it is 1 / n times (n: natural number), the portion other than the wiring will also be measured. In this case, the measurement takes some time, but since the components other than the wiring, that is, the background is also measured, the contrast of the wiring with respect to the background can be standardized. Since the contrast of good and bad wiring is not always the same,
By normalizing, failure analysis can be performed more accurately.

If the lattice spacing is set to m / n times (m> n), the wirings are interleaved for measurement. m when n = 1
It is a multiple, that is, an integer multiple, and when n ≠ 1, it is 3/2 times, 4
It is a fractional multiple, such as / 3 times. Usually, failure analysis starts with measuring the integrated circuit at low magnification (that is, measuring a wide area).
The faulty part is roughly registered, and the registered part is measured at a high magnification (that is, a narrow area is measured) to analyze the accurate position. However, when measuring at a low magnification, the lattice spacing is m / n. By doubling the measurement, it is possible to roughly estimate the faulty part, and at this time, the measurement time is shortened and the efficiency is improved.
Efficient and highly accurate measurement can be performed by making the lattice spacing m / n times when measuring at low magnification and 1 / n times when measuring at high magnification.

In the embodiment, the difference between the potential contrast images of the non-defective product and the defective product is taken, but it is obvious that the potential contrast image of the integrated circuit to be measured and the design data may be compared.

As described above, the failure analysis method according to the present embodiment is a method of obtaining information in a two-dimensional lattice-like point series rather than extracting information of a two-dimensional surface of an integrated circuit as in the conventional case. .. In other words, the surface information is replaced with point information, and the speed at which information is obtained is hundreds of times faster, and the ambiguity of failure judgment due to the overlay misalignment of image images that was conventionally achieved when comparing good and defective products. It has the effect that the problem of is avoided.

FIG. 22 is a diagram showing the concept of the configuration on the CRT of the workstation in the method of using the mouse pointer to associate the positions of the DFI image and the optical microscope image. The DFI image (defective product image, non-defective product image, failure image) 4 and the optical microscope image 5 are displayed in separate windows 2 and 3 on the CRT screen 1 of the workstation. By designating an arbitrary location of 4, another pointer 7 points to the corresponding location on the optical microscope image 5. (2) On the contrary, by designating an arbitrary position on the optical microscope image 5 with the pointer 7, another pointer 6 is moved to the DF
By pointing to the corresponding location on the I-image 4, the DFI
Assist in navigation of failure points in the method.

When pointing to the corresponding portion, the pointer 6,
The sample stage or the display position of the image data is automatically moved so that the position 7 is always the specified position in the windows 2 and 3.

FIG. 23 is a diagram showing the concept of the configuration on the CRT of the workstation in the method of performing navigation by superimposing the DFI failure image on the optical microscope image. The DFI image (failure image) 4 and the optical microscope image 5 are displayed in the same window 2 on the CRT screen 1 of the workstation, and the DFI image is made semitransparent and the failure image 4 is superimposed on the optical microscope image 5. By matching them, the connection information of the wirings and elements on the optical microscope image 5 is known, and the navigation of the failure location by the DFI method is supported.

As described above, the present invention relates to a method of narrowing down a failure location by using a probing method such as an electron beam testing method when analyzing a defective product or a defective product of a semiconductor integrated circuit. Has been described in detail by taking the DFI method, which is one of the methods for narrowing down the failure location, by obtaining the image in the form of an image. In this way, by linking the optical microscope image information and the image obtained by probing, the efficiency of narrowing down the defective portion can be measured.

According to the navigation method shown in FIGS. 22 and 23, (1) it is sufficient to capture the optical microscope image of the chip itself to be analyzed, and the user can easily obtain it. (2) It is relatively easy to maintain both software and hardware interfaces. (3) It is possible to easily obtain the positional information of not only the uppermost layer but also the lower wiring and the diffusion layer. And the like.

[0051]

As described above, according to the present invention, EB irradiation is not performed on the entire surface sweep by EB but only on the coordinate points selected in advance, so that the failure analysis can be completed in a short time. ..

[Brief description of drawings]

FIG. 1 is a block diagram showing an apparatus used in a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a conventional analysis method.

FIG. 3 is a flowchart showing a procedure of the first embodiment.

FIG. 4 is a circuit diagram showing an analysis target of the first embodiment.

5 is a layout diagram of the circuit shown in FIG.

6 is a pattern diagram showing wirings of different potentials in the layout shown in FIG.

7 is a cross-sectional view showing a structure on a semiconductor substrate of the circuit shown in FIG.

8 is a graph showing the intensity of secondary electrons obtained when the structure shown in FIG. 7 is irradiated with EB.

FIG. 9 is a front view showing a display on the display of the first embodiment.

FIG. 10 is a diagram illustrating a method of dividing wiring data according to the first embodiment.

FIG. 11 is a circuit diagram showing a circuit to be analyzed in the second embodiment of the present invention.

FIG. 12 is a layout diagram of the circuit shown in FIG. 11.

13 is a pattern diagram showing wirings of different potentials in the layout shown in FIG.

FIG. 14 is a diagram showing EB irradiation positions of the first layer wiring shown in FIG.

FIG. 15 is a diagram showing EB irradiation positions of the second layer wiring shown in FIG.

16 is a diagram showing another EB irradiation position of the wiring shown in FIG.

FIG. 17 is a flowchart showing an analysis procedure of the second embodiment.

FIG. 18 is a front view showing a display on the display of the second embodiment.

FIG. 19 is a diagram showing EB irradiation positions in the third embodiment.

FIG. 20 is a diagram showing a relationship between EB irradiation positions and wirings according to the third embodiment.

FIG. 21 is a diagram illustrating a difference in potential between a non-defective product and a defective product.

FIG. 22 is a front view showing a display on the workstation.

FIG. 23 is a front view showing another display on the workstation.

[Explanation of symbols]

 1,2,3 EB 1 ', 2', 3 'secondary electron 31 high potential wiring 32 low potential wiring 41,61 EB irradiation point 101 lens barrel 102 EB generator 103 LSI 104 test board 105 XY stage 106 secondary electron Detector 107 LSI tester 108 XY stage drive circuit 109 CPU 110 Beam pulse control device 111 CRT

 ─────────────────────────────────────────────────── ─── Continuation of the front page (31) Priority claim number Japanese patent application No. 3-81185 (32) Priority date Hei 3 (1991) March 22 (33) Priority claim country Japan (JP)

Claims (13)

[Claims] 1. An electron beam generator for irradiating an integrated circuit device including a plurality of wirings having different depths from the surface with an electron beam, and a secondary electron beam generated in the integrated circuit device during electron beam irradiation. In a failure analysis device for an integrated circuit device, which includes a detector and a position control means for controlling an irradiation position of an electric beam on the integrated circuit device, a failure analysis device from the surface of the plurality of wirings based on the intensity difference of the secondary electron beam. A failure analysis device for an integrated circuit device, characterized in that a difference in depth is judged and a wiring pattern showing the difference in depth from the surface is displayed on a monitor screen based on the judgment result. 2. A failure analysis method for an integrated circuit device including a plurality of wirings having different depths from the surface, wherein the step of irradiating the plurality of wirings with an electron beam and the difference in the depth from the surface of the wirings. A failure analysis method for an integrated circuit device, comprising: forming a potential contrast image based on a corresponding secondary electron beam intensity distribution; and forming layout data based on the potential contrast image and displaying the layout data as a monitor screen. 3. The electron beam is applied to a preselected point of the plurality of wirings, and the selected point is selected from points on the wiring that can be reached by an electron beam except for the overlapping portion of the wirings. Item 2. An integrated circuit device failure analysis method according to Item 2. 4. The potential contrast image is formed for each of a fault-free integrated circuit device and a faulty integrated circuit device, and the formed potential contrast images are compared to find a fault based on a difference in point potential. Claim 3
A failure analysis method for an integrated circuit device according to claim 1. 5. The failure analysis method for an integrated circuit device according to claim 4, wherein an image representing a failure position is formed based on the information indicating the difference in point potential, and the image is superimposed and displayed on the monitor screen. 6. An electron beam reachable point is selected from each of the wiring groups by dividing the plurality of wires into a wiring group electrically connected to each other, and selecting one reachable point of the selected electron beam. An electron beam is irradiated to each of the two.
A method for failure of the integrated circuit device described. 7. The potential contrast image is formed for each of the fault-free integrated circuit device and the faulty integrated circuit device, and the formed potential contrast images are compared to find a fault based on a difference in point potential. Claim 6
A failure analysis method for an integrated circuit device according to claim 1. 8. The failure analysis method for an integrated circuit device according to claim 7, wherein an image representing a failure position is formed based on the information indicating the difference in the point potential, and the image is superimposed and displayed on the monitor screen. 9. The failure analysis method for an integrated circuit device according to claim 2, wherein the electron beam is applied to each lattice point forming a two-dimensional lattice point on the surface of the integrated circuit device. 10. The lattice point spacing of the two-dimensional lattice points is 1 / n times or m / the wiring spacing included in the integrated circuit device.
The failure analysis method for an integrated circuit device according to claim 9, wherein n times, m and n are natural numbers, and m is larger than n. 11. The potential contrast image is formed for each of a fault-free integrated circuit device and a faulty integrated circuit device, and the formed potential contrast images are compared to find a fault based on a difference in point potential. 11. A failure analysis method for an integrated circuit device according to claim 10. 12. The failure analysis method for an integrated circuit device according to claim 11, wherein an image representing a failure position is formed based on the information indicating the difference in the point potential, and the image is superimposed and displayed on the monitor screen. 13. A failure analysis of an integrated circuit device according to claim 5, 8 or 12, wherein an optical microscope image showing a circuit pattern of the semiconductor integrated circuit device and an image showing the failure position are displayed in parallel in association with each other. Method.