JP2009302403A - Defect analysis method for semiconductor device and defect analysis method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a defect analysis method for a semiconductor device that takes defect analysis of a plurality of devices formed on a wafer with high precision. <P>SOLUTION: A test area table is generated which relates design data of a circuit block, shipment test data, and manufacturing process test data, a circuit block corresponding to a defect place in a shipment test and a failure place of manufacturing process test data are compared with each other, and data in the test area table corresponding to an area where the defect place and the failure place overlap with each other is selected. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a semiconductor device failure analysis method and a semiconductor device failure analysis system, and more particularly to a semiconductor device failure analysis method formed on a wafer and a failure analysis system thereof.

A semiconductor device is formed through a plurality of processes such as an ion implantation process, a film forming process, and a patterning process. A plurality of semiconductor devices are arranged vertically and horizontally on a semiconductor wafer, and after the final process, the semiconductor devices are cut and divided into chips.

In various processes on a semiconductor wafer, defects occur due to adhesion of residues, dust, etc., patterning defects, and the like. An operation failure occurs in a semiconductor device having a pattern defect.
Therefore, in order to investigate the cause of the occurrence of a defect, for example, the following failure analysis system is known.

One failure analysis system first tests circuit blocks in a plurality of semiconductor wafers with a logic tester, and associates the test results with wafer numbers and XY coordinates in the chip. Further, the failure analysis system creates defective circuit block information based on the pass / fail result by the test, expresses the result as yield information, and outputs the information to the display unit in units of circuit blocks.

Another defect analysis system first calculates defect coordinates in a chip area of a defective circuit block based on arrangement information of a plurality of circuit blocks arranged in the chip and defect information of the circuit block. Further, the defect analysis system calculates the defect coordinates in the wafer based on the defect coordinates in the chip area and the exposure position information, and maps and displays the defect coordinates in the wafer according to the physical coordinates on the wafer surface. Further, the feature amount of the arc outer periphery defect is calculated to classify the defect mode.
JP 2004-31676 A JP 2006-344785 A

An object of the present invention is to provide a semiconductor device failure analysis method and a semiconductor device failure analysis system capable of performing failure analysis with high accuracy.

According to one aspect of the present invention, a step of acquiring design data including area data indicating positions of circuit blocks in a plurality of semiconductor devices formed on a wafer and data of layers constituting the circuit blocks from a database; A step of obtaining shipment test data including test item data in a shipment test performed on the semiconductor device from the database; and a manufacturing process test data including layer test data of the layer performed in the manufacturing step of the semiconductor device. A step of obtaining from the database; a step of creating a test area table associating the design data, the shipment test data, and the manufacturing process test data of the circuit block; and the circuit block corresponding to a defective portion by the shipment test. And the process of comparing with the defective part of the manufacturing process test data, and the defective part Failure analysis method of a semiconductor device characterized by having the steps of displaying on the output section data based on the test area table of area where the defective portion overlap is provided.
According to another aspect of the present invention, a step of acquiring layer data based on a process test result in a manufacturing process from a database in a storage unit for a plurality of layers constituting a circuit block in a semiconductor device formed on a wafer. A step of calculating a defect contribution ratio indicating a contribution ratio of defect occurrence of the circuit block for each of the plurality of layers of the layer data, and test data for shipping the wafer stored in the storage unit. A step of obtaining a defect occurrence rate for each of the circuit blocks in the semiconductor device from a stored shipping test result database in the storage unit, and for each of the plurality of layers, the defect contribution rate is integrated with the defect occurrence rate And calculating an integrated value, calculating a total sum of the integrated values for each layer, and outputting a calculation result to an output unit. That failure analysis method of a semiconductor device is provided.
According to still another aspect of the present invention, a first memory for storing area data indicating positions of circuit blocks in a plurality of semiconductor devices formed on a wafer and design data including data of layers constituting the circuit blocks. A manufacturing process test including a layer test data of the layer obtained in the manufacturing process of the semiconductor device, a second storage unit storing shipping test data including test item data in a shipping test performed on the semiconductor device A third storage unit that stores data; a data processing unit that creates a test area table that associates the design data of the circuit block, the shipping test data, and the manufacturing process test data; and the shipping test data includes the data processing unit By comparing the defective portion of the circuit block with the defective portion of the circuit block included in the manufacturing process test data, the defective portion What is claimed is: 1. A defect analysis system for a semiconductor device, comprising: a comparison processing unit that selects data based on the test region table in a region where the defect part overlaps; and an output unit that displays a comparison result by the comparison processing unit. Provided.

According to the present invention, a test area table that associates design data, shipping test data, and manufacturing process test data of circuit blocks that constitute a semiconductor device formed on a wafer is created, and a defective portion and manufacturing process test data by a shipping test are created. Compared with the defective part, the data of the test area table is selected for the area where the defective part and the defective part overlap.
This makes it easy to analyze defects by identifying the areas where defects occur in the shipment test and manufacturing process test for each circuit block in the semiconductor device on the wafer, and analyzing the data in the test area table for those areas become.

Embodiments of the present invention will be described below in detail with reference to the drawings.
FIG. 1 is a configuration diagram showing a failure analysis system according to an embodiment of the present invention.
The failure analysis system shown in FIG. 1 has a computer 1, and the computer 1 has C
A PU, a storage unit, and other devices are connected to each other via a data bus. Further, an external peripheral device such as an operation device represented by a keyboard 1a and a mouse 1b, an output device represented by a printer 1d, and the like is connected to the data bus in the computer 1 through an interface (not shown). Has been. The computer 1 is installed with an OS, application software, and the like. The application software includes failure analysis software for performing failure analysis of an apparatus (device) as described below.

The computer 1 is connected to a network 2 such as a LAN via an interface, a hub, or the like, for example. The network 2 is in a state where it can be connected to a database in the storage devices 3 to 7 stored in another computer or server. The database includes not only design data necessary for manufacturing the semiconductor device but also measurement data during the manufacturing of the semiconductor device and measurement data after the manufacturing.

The test object is a plurality of semiconductor devices 12 formed on the semiconductor wafer 11 shown in FIG.
In the semiconductor device 12, for example, as shown in FIG. 3, a plurality of circuit blocks that realize a predetermined function are arranged. The shape of the layers constituting the circuit block, the composition of materials, etc. are stored in the fourth storage device 6 as a design information database.

The circuit block shown in FIG. 3 is exemplified as follows.
That is, the hard IP macroblock 13a provided as a GDSII file to the user, and the first and second provided in the register transfer level (RTL) code format that can be synthesized.
, Third and fourth soft macroblocks 13b, 13c, 13d, and 13e are shown. Further, an IO macro block 13f that interfaces with an external device, an analog macro block 13g that is an analog circuit, and first, second, and third memory blocks 13h, 13i, and 13j such as a RAM are shown. .

The first memory block 13h is arranged as an independent circuit block, and the second and third memory blocks 13i and 13j are formed as circuit blocks in a hierarchy below the first soft macroblock 12b.
The fourth soft macro block 13e is arranged as a circuit block in a layer below the third soft macro block 13d.

The GDSII file of the hard IP macroblock 13a is stream layout IC layout data.
In such a semiconductor device 12, a semiconductor active element and a semiconductor passive element are formed for each circuit block 13a to 13j or for each function of the circuit block 13a to 13j, for example, and a test circuit is included therein. Yes.

Some test circuits are reused as circuit block functions, and others have individual functions for circuit blocks due to demands for high-speed operation, and are generally controlled by the master test controller at the top level. It's getting on. Such a configuration is, for example, IEEE
It will conform to the standard 1500 embedded core test.

The area of such circuit blocks 13a to 13j is smaller than that of the entire semiconductor device 12, and few layers are used. For this reason, in the failure analysis, it is important to narrow down the failure by specifying the failure of the circuit block by the test circuit.
As shown in FIG. 2, a plurality of semiconductor devices 12 are formed vertically and horizontally along the surface of the semiconductor wafer 11, and finally separated into chips by a dicing saw or the like. The semiconductor device 12 before separation in the semiconductor wafer 11 is also referred to as a semiconductor chip region below.

The test contents for the semiconductor device 12 include items and categories that are measured in a predetermined process of manufacturing the semiconductor device, items that are measured after the semiconductor device 12 is completed, categories, and the like. First and second storage devices 3,
4 is stored.

As a database for analyzing defects of the semiconductor device 12, for example, a defect inspection information database stored in the first storage device 3, a shipment test map information database stored in the second storage device 4, and a third There is a block information database stored in the storage device 5.
The defect inspection information database is data based on inspection after a predetermined process in the manufacture of the semiconductor device 12, and is based on the test results measured in the formation process of the semiconductor pattern, the conductive pattern, the insulating pattern, etc. constituting the semiconductor device 12. Based data.

In addition to the plurality of layers formed on the semiconductor wafer 11, the lot number of the semiconductor wafer processed in the semiconductor manufacturing process, the number of the semiconductor wafer 11 in the lot, and the database formed based on the inspection result of the manufacturing process The number of the layer to be tested, test items,
XY coordinates on the semiconductor wafer 11 and the like are stored and associated with each other.
The database based on the inspection result includes defect modes, and further includes a scanning electron microscope (SE
M) Image data such as photographs is also included.

The test map information database includes a plurality of semiconductor devices 12 already formed on the semiconductor wafer 11.
Is a shipping test database storing information on electrical test results before shipping. The test map information database includes information in which the test items, categories, and subcategories in each semiconductor device 12 in the semiconductor wafer 11 are associated with circuit blocks and XY coordinates with respect to good and bad results.
Further, the test map information database includes, for example, a lot number of a semiconductor wafer subjected to a shipment test, a wafer number in the lot, and a semiconductor device number in the wafer in association with the shipment test data. .

The block information database is information obtained by extracting from a database of design information stored in the fourth storage device 6 and a database such as test generation information stored in the fifth storage device 7. As a database of design information, for example, there is design information of the semiconductor device 12 and circuit blocks therein. The test generation information includes, for example, information on circuit blocks used as test targets, electrical circuits such as test elements, layer structures, and patterns.
The storage area of the database is not limited to the first to fifth storage devices 3 to 7, but may be a single storage device or a storage device in the computer 1.

Next, the flow of the failure analysis system will be described with reference to FIGS.
First, as shown in FIG. 4, the computer 1 follows the operation of the keyboard 1a and the like,
Design information data and test generation information data are acquired from the fifth storage devices 6 and 7. Further, the computer 1 functions and arrangements of circuit blocks in the semiconductor device area 12, test element areas,
The layer-by-layer integration information is extracted to generate a test area table, which is stored in the block information database 5.

The test area table has a configuration shown in FIG. 6, for example. In FIG. 6, the test items corresponding to the function of the circuit block, such as a pin contact (PIN CONTACT) test, a logic Bist test, and a memory Bist test, are shown. It is not something that can be done.
The vist is a built-in self test, which is a circuit that generates test data for testing the presence or absence of a failure of the circuit under test and compares it with expected value data. A semiconductor circuit formed in the semiconductor device 12 is used. The The semiconductor circuit may be an entire circuit block, a part of the semiconductor element, or a test element.

Further, the test area table is provided with a layer-by-layer information column corresponding to each test item. The layer-by-layer integration information is information on all or part of a plurality of layers (Layer 0 to 5) constituting the semiconductor device 12, such as a polysilicon layer and a metal layer. As stratification density information,
In this embodiment, a value obtained by calculating a sensing area (Critical Area; CA) assumed for each of Layers 0 to 5 for each circuit block to be tested will be described as an example.

The sensing area is an area obtained by sensing area (critical area) analysis, and causes an actual failure such as an element in a semiconductor device, such as a wiring or a via, being opened or short-circuited due to a manufacturing defect. The sum of the areas of the parts, based on calculation by software. The larger the value of the sensing area, the higher the probability that the layer will be defective due to a defect.

Since the test area table is generated for each type of semiconductor device 12 and stored in the third storage device 5 for the block information database or the storage device in the computer 1, it can be reused thereafter. There is no need to create it. In this case, the computer 1 acquires a test area table as necessary.
For failure analysis, first, the computer 1 acquires shipping test data from the test map information database in the second storage device 4 through the network 2 as shown in I and II of FIG. To create a test map.

As illustrated in FIG. 7, the test map displays the defective portion R based on the above-described shipping test data on the display 1 c in correspondence with the coordinates of the semiconductor wafer 11 and maps the position of the semiconductor device 12 where the defect has occurred. It is a map for displaying in a shape. The test map is created for each of the semiconductor wafers 11 for test categories and subcategories, for example, IO macroblocks and logic vist, with respect to operations and characteristics, and defects.

Next, as shown in III of FIG. 5, the computer 1 reads the test area table shown in FIG. 6 for each semiconductor device 12 to be tested, and writes the test data in the test area table. Each of the test targets is a block name of a circuit block (Block

Name).

In the test area table shown in FIG. 6, the test item is a test item (Test Item).
), Sub Item (sometimes called Test Block or Test Domain)
It is shown. For example, the test items include pin contacts, which are the types of tests,
A logic vist and a memory vist are shown. The sub-item indicates a specific test target of the test item. For example, when the test item is a pin contact, the test object is indicated by sub items IO1, 2,.
A test object that is a sub-item is specified by a block name and area data in a field of an area of the test area table. For example, the block name of the subitem IO1 is IOCELLI.

Further, the area data in which the test item of the sub item exists is indicated by an XY coordinate as a rectangular area in the semiconductor device 12. That is, as illustrated in FIGS. 8A and 8B, the rectangular area 1
3x is indicated by specifying two opposing vertices, that is, a base point and an end point. Note that the base point and the end point are indicated by X-coordinate and Y-coordinate, for example, (a0, b0), (c0, d0), etc. in the test area table of FIG.
The computer 1 records the CA values of the plurality of layers constituting the circuit blocks 13a to 13j to be tested in Layers 0 to 5 in the column of layered integrated information in FIG. Further, if a defect exists in the sub-item from the result of the shipment test, a flag of defective shipment test is set for the defective sub-item.

Next, as shown in IV of FIG. 5, the computer 1 acquires the position of the circuit block to be tested and the test items from the fourth and fifth storage devices 6 and 7, and is illustrated in FIG. 9A. In this manner, a circuit block is added to the semiconductor device 12 on the display 1c and displayed.
Further, an item having a defect flag in the test area table is extracted, and a defect area map is created and displayed for each circuit block in the semiconductor device 12. The circuit block having the defective area in FIG. 9A is identified and displayed by the shading in FIG. 9B.

Accordingly, in FIG. 7, the defective portion is displayed for each semiconductor device 11 based on the shipping test result, whereas in FIGS. 9A and 9B, the defective portion R is circuitized based on the test area table. Visibility can be improved by displaying each block.
By the way, as shown in FIG. 3, second and third memory blocks 13i and 13j of lower layers are formed in the first soft block 13b, and the third soft block 13 is also formed.
A lower fourth soft block 13e is formed in d. In such a circuit block configuration, the test results of both the upper and lower circuit blocks may be defective.

In such a case, the defect of the circuit block in the lower hierarchy is preferentially displayed on the map, and the defect of the circuit block in the upper hierarchy is not displayed. In this way, by narrowing down the defective area,
Defect collation accuracy can be increased.
The processing for the test area table as described above is performed by the computer 1 based on the data processing function of the defect analysis software. Note that the test area table does not necessarily have to be output by the display 1c, the printer 1d, or the like, as shown in FIG. 6, and may be in a state of being associated in the storage device of the computer 1.
Next, based on the operation of the keyboard 1a or the like, the computer 1 obtains the yield influence degree of the semiconductor device 11 as shown by V and VI in FIG. As the yield influence degree, the defect contribution rate will be described as an example.

The defect contribution rate is determined when a defect occurs in a circuit block constituting the semiconductor device 12.
This is the ratio at which the layers constituting the circuit block contribute to defects.
The defect contribution rate is obtained based on the CA rate calculated from the CA value shown in the column of layer-by-layer integration information in the test area table shown in FIG. 6 and the defect occurrence rate for each of the circuit blocks 13a to 13f.

Here, the CA rate is the C per layer with respect to the sum of the CA values of a plurality of layers constituting the circuit block.
It is the ratio of A value. The defect occurrence rate of the circuit block is a ratio of occurrence of defects for a predetermined circuit block calculated based on the shipping test result of the plurality of semiconductor devices 12.
Table 1 below shows the defect occurrence rate of the circuit blocks 100, 200, and 300 included in the semiconductor device, and the CA of each of the layers A, B, C, and D constituting the circuit blocks 100, 200, and 300. And the defect contribution rates of the layers A, B, C, and D are shown.

The CA rate is determined in each of the circuit blocks 100, 200, and 300 by using layers A, B, C,
The ratio of the CA value of each layer A, B, C, D to the sum of the respective CA values of D is shown.
In addition, the defect contribution ratio is the CA ratio of each layer A, B, C, D shown in Table 1 and each circuit block 1.
After the defect occurrence rates of 00, 200, and 300 are integrated with each other, the integrated values are expressed as layers A, B, C,
The total value is shown for each D.

For example, in the example shown in Table 1, the defect occurrence rate α of the blocks 100, 200, and 300 is 25%.
10%, 5%, and layer A (Layer A) C for blocks 100, 200, 300
The A rate β is 50%, 25%, and 40%. In this case, the defect contribution rate P (A) of the layer A is calculated by the following formula to be 17%.
P (A) = Σ (α × β) = 25% × 5% + 10% × 25% + 5% × 40% = 17%

Similarly, the defect contribution rate is obtained for the layers B, C, and D, and the layers A, B, C, and D are shown in the graph as shown in FIG.
The larger the defect rate contribution rate, the higher the probability of causing a defect. Therefore, in the example shown in Table 1 and FIG. 10, since the layer A is considered to be the largest cause of defects in the semiconductor device, it is important to investigate the formation conditions and patterning conditions of the layer A.

The yield influence degree can be used for defect analysis by itself. In this case, the calculation of the yield influence degree is performed by the computer 1 based on the data processing function of the defect analysis software. The result can be output to the display 1c and the printer 1d by the computer 1 as a map or as a numerical value in association with circuit blocks and constituent layers.

Next, as shown at VII in FIG. 5, the computer 1 selects a random failure factor by removing the system failure factor from the failure factors of the circuit blocks constituting the semiconductor device. The system failure is a failure whose cause is obvious in a circuit test, a test environment, and a device characteristic test in a shipping test.

As a system failure, for example, as shown in a black square IO macroblock 13f in a region surrounded by a broken line in FIG. 11, there is a failure in which an IO failure due to contact resistance at the time of a shipping test appears continuously adjacently. is there. In addition, as a system failure, there is an SRAM failure caused by a characteristic test performed in a shipping test, for example, an operation failure in which an applied voltage is generated near the upper limit or the lower limit of the recommended operating conditions. As such an operation failure, for example, in the black square second and third memory blocks 13i and 13j in the region surrounded by the broken line in FIG.

When there is a system failure, the computer 1 selectively displays only such specific test items on the display 1c or outputs it to the printer 1d to grasp the tendency of defects in the surface of the semiconductor wafer 11. As a result, it is possible for a person to recognize whether or not the system is defective.
The system failure is not caused by a random defect, but becomes a noise component at the time of defect verification. Therefore, the operator removes the system failure from the failure data, or the computer 1 automatically detects the failure of the specific test item from the failure data. To remove.

Thus, by removing the system failure from the failure factor, a random defect in the failure data becomes clear.
Extraction of random defects as described above is performed for each semiconductor device 12 in the semiconductor wafer 11. Further, the position of the random defect is indicated by coordinates in the semiconductor device 12 based on the test area table shown in FIG.

Therefore, as shown in VIII of FIG. 5, the computer arranges each semiconductor device 12 in order to align the coordinates of the plurality of semiconductor devices 12 in one semiconductor wafer 11 with the defect inspection information database in the first storage device. Are converted into XY coordinates on the wafer.
Next, as shown by IX in FIG. 5, the computer 1 extracts from the first storage device 3 coordinate data of defects obtained by inspection in the manufacturing process of the semiconductor device. In the defect coordinate data, the distribution of a predetermined defect on the semiconductor wafer 11 and its center of gravity are indicated by XY coordinates.

Subsequently, as shown by X in FIG. 5, the computer 1 compares the defect coordinate data acquired from the manufacturing process test data with the random defect coordinate data of the shipping test based on the comparison processing function of the defect analysis software. Perform collation analysis. The defect matching analysis is performed by the computer 1 as follows, for example.
When a random defect exists in the test item shown in the test area table, a block in which the random defect exists is indicated by a shaded base in FIG.

In FIG. 8A, when the center of gravity of the defect according to the defect inspection database indicated by the black circle is present in the rectangular area 13x of the block including the random defect, the defect is a killer defect (
It is determined that the defect has actually contributed to the defect. Then, the position of the killer defect is displayed on the display 1d and further output to the printer 1e (XI in FIG. 5).
On the other hand, as shown by the white circle in FIG. 8A, when the center of gravity of the defect in the defect inspection database is outside the rectangular area 13x of the block including the random defect, it is determined that the random defect is not a killer defect. To do. In this case, the computer 1 displays its presence on the display 1c.
Does not display.

Further, even when the center of gravity of the defect in the defect inspection data exists at the edge of the pattern indicated by the shaded area in FIG. 8B, the defect is determined to be a killer defect.
If the position of the killer defect is found in this way, for example, C in the test area table shown in FIG.
It becomes easy to find out the cause of occurrence of the killer result by analyzing the defect contribution rate data calculated based on the A value and the CA value.

As described above, according to the present embodiment, after associating the test items for the circuit blocks included in the semiconductor device, the test target area, and the data of the constituent layers, the test items that become defective based on the shipping test from those data, The data of the test target area and the constituent layers are selected.
Then, for the selected data, after converting the coordinates of the circuit block in the semiconductor device to the coordinates of the semiconductor wafer, the defect coordinate data on the semiconductor wafer, for example, the coordinate data of the center of gravity of the distribution of layer defects is obtained from the test result in the manufacturing process. Extract. After that, the defect coordinates based on the shipping test and the defect coordinates based on the process test are collated.

Thereby, the accuracy of the information specifying the cause of the defect can be improved by comparing the shipment test result and the process test result not with the unit of the semiconductor device in the semiconductor wafer but with the unit of the circuit block in the semiconductor device.
In addition, the test results include defect data of layers constituting the circuit block, for example, the sensing area (C
Since A) is included, it is easy to specify a layer that contributes to the generation of defects.

Further, according to the present embodiment, since the system failure data that can easily estimate the cause of the failure is removed from the shipping test result data, it becomes easy to investigate the cause of the random defect.

In addition, when a circuit block in the lower hierarchy is included in the circuit block, the defect of the circuit block in the lower hierarchy is extracted with priority over the circuit block in the upper hierarchy. It is possible to narrow down and improve the accuracy of defect analysis.
In addition, since the defect contribution rate is obtained for a plurality of layers constituting the circuit block, the cause of the result can be analyzed in descending order of the defect contribution rate, and the cause of the defect occurrence can be detected early.

By the way, it is also conceivable to identify the killer defect by collating the coordinates between the defect inspection data by the manufacturing process test and the shipment test data for each semiconductor device. Further, defect inspection data may be collated with respect to RAM fail bit map (FBM) information to identify a killer defect, or an estimated net obtained by logic fault diagnosis and defect inspection data may be collated. Killer defects may be identified.

However, the defect data collation method for each semiconductor device has a problem that the failure analysis accuracy is lowered due to an increase in the chip size of the semiconductor device due to high functionality / high integration. Further, in the case of collation analysis using RAM, when the number of layers in the layer structure is increased, it is difficult to specify a defect caused by the upper layer. Further, in the case of collation analysis using logic failure diagnosis, there is a problem that failure diagnosis time is required.

On the other hand, in the present invention, the shipping test and process test data for each circuit block is compared, and defect information of each layer constituting the test target circuit is acquired and associated with the test data, thereby causing the layer. It becomes easy to identify defects.
By the way, although the defect analysis system and the defect analysis method have been described for the application of a plurality of semiconductor devices formed on a semiconductor wafer, a plurality of defect analysis systems and defect analysis methods are formed on a wafer like a reproduction and recording head formed on a plurality of Altic wafers. You may apply about various apparatuses.

The present invention has been described in detail in the above embodiments. However, it will be apparent that there are various aspects and modifications that do not depart from the spirit and scope of the invention. For example, the detailed order or combination of processes described herein is merely illustrative, and the invention may be used in different or additional processes, or in different combinations or orders. In addition, for example,
Each feature in one embodiment can be mixed and matched with other features in other embodiments. Features may additionally be added or removed on demand as well. Accordingly, the invention is not limited except in terms of the appended claims and their corresponding patents.

Next, embodiments of the present invention will be further described.
(Appendix 1)
Obtaining from the database design data including area data indicating positions of circuit blocks in a semiconductor device formed on a wafer and data of layers constituting the circuit blocks;
A step of obtaining shipment test data including test item data in a shipment test performed on the semiconductor device from the database; and a manufacturing process test data including layer test data of the layer performed in the manufacturing step of the semiconductor device. Obtaining from the database;
A step of creating a test area table associating the design data of the circuit block, the shipping test data, and the manufacturing process test data; and a defect in the circuit block corresponding to the defective portion by the shipping test and the manufacturing process test data. And a step of displaying, on an output unit, data based on the test region table of a region where the defective portion and the defective portion overlap each other, and a method for analyzing a failure of a semiconductor device.
(Appendix 2)
2. The failure analysis method according to appendix 1, wherein the display on the output unit is performed by selecting the test item data from the manufacturing process test data.
(Appendix 3)
The defect analysis method according to appendix 1 or appendix 2, wherein the test for the circuit block test element is performed as the shipping test.
(Appendix 4)
The step of writing to the test region table includes the step of writing the region data of the circuit block that is the subject of the shipment test among the shipment test data, the step of writing the test item data for the circuit block, And writing the layer test data of the circuit block.
(Appendix 5)
The circuit block includes an upper layer circuit block in an upper layer and a lower layer circuit block in a lower layer, and the defective portion and the failure portion are compared with each other in the lower layer circuit block. The defect analysis method according to any one of appendix 4.
(Appendix 6)
6. The failure analysis method for a semiconductor device according to any one of attachments 1 to 5, wherein the failure portion is data obtained by removing system failure data in which the cause of failure is obvious.
(Appendix 7)
The component layer data is a sensing area for a plurality of component layers.
Or a failure analysis method for a semiconductor device according to appendix 6.
(Appendix 8)
A step of obtaining layer data based on a process test result in a manufacturing process from a database of a storage unit for a plurality of layers constituting a circuit block in a semiconductor device formed on a wafer; and the plurality of layers among the layer data A step of calculating a defect contribution rate indicating a contribution ratio of the occurrence of a defect in the circuit block for each of the above, and a shipment test result in the storage unit storing test data for shipping the wafer stored in the storage unit Obtaining a defect occurrence rate for each of the circuit blocks in the semiconductor device from a database; and for each of the plurality of layers, integrating the defect contribution rate to the defect occurrence rate to obtain an integrated value; A method of analyzing a failure of a semiconductor device, comprising: calculating a total sum of the integrated values of the output and outputting a calculation result to an output unit .
(Appendix 9)
A first storage unit for storing area data indicating positions of circuit blocks in a semiconductor device formed on a plurality of wafers and design data including data of layers constituting the circuit blocks;
A second storage unit that stores shipping test data including test item data in a shipping test performed on the semiconductor device, and manufacturing process test data including layer test data of the layer acquired in the manufacturing process of the semiconductor device A third storage unit, a data processing unit that creates a test area table that associates the design data, the shipment test data, and the manufacturing process test data of the circuit block, and the circuit block included in the shipment test data. A comparison processing unit that selects data based on the test area table of an area where the defective part and the defective part overlap by comparing the defective part and the defective part of the circuit block included in the manufacturing process test data; and An output unit for displaying a comparison result by the comparison processing unit, Beam.
(Appendix 10)
The data processing unit acquires, from the first storage unit, the area data of the circuit block that is the object of the shipping test from the shipping test data, writes the area data in the test area table, and the test for the circuit block Item data is acquired from the second storage unit and written to the test region table, the layer test data of the circuit block is acquired from the third storage unit and written to the test region table, and the comparison processing unit is 5. The semiconductor device failure analysis system according to claim 4, wherein the defective portion and the defective portion are compared for each test item data of the circuit block.
(Appendix 11)
11. The semiconductor device failure analysis system according to appendix 9 or appendix 10, wherein the shipping test is a test performed on a test circuit of the circuit block.
(Appendix 12)
Any one of appendix 9 to appendix 11 wherein the layer test data is a sensing area
Defect analysis system for semiconductor devices described in 1.
(Appendix 13)
13. The semiconductor device failure analysis system according to appendix 12, wherein the data processing unit has a structure for calculating a probability of contributing to the failure of the failure location based on the shipping test data based on the sensing area.
(Appendix 14)
14. The semiconductor device failure analysis system according to any one of Supplementary Note 9 to Supplementary Note 13, wherein the defective portion is data from which a system failure with a clear cause of failure is removed.
(Appendix 15)
The comparison processing unit has a structure in which the circuit block having the upper layer circuit block of the upper layer and the lower layer circuit block of the lower layer has a structure for comparing the defective portion and the failure portion with respect to the lower layer circuit block. 15. The failure analysis system for a semiconductor device according to any one of appendix 9 to appendix 14, characterized by:

FIG. 1 is a block diagram showing the apparatus configuration of a failure analysis method and system according to an embodiment of the present invention. FIG. 2 is a plan view showing a semiconductor wafer to be tested applied to the failure analysis method and system according to the embodiment of the present invention. FIG. 3 is a diagram showing a layout of blocks in the semiconductor device to be tested applied to the failure analysis method and system according to the embodiment of the present invention. FIG. 4 is a first flowchart showing a failure analysis method and system according to an embodiment of the present invention. FIG. 5 is a second flowchart showing the failure analysis method and system according to the embodiment of the present invention. FIG. 6 is a test area table used in the failure analysis method and system according to the embodiment of the present invention. FIG. 7 is a map of the semiconductor device in the semiconductor wafer displayed by the failure analysis method and system according to the embodiment of the present invention. FIG. 8 is a diagram showing test target areas acquired by the failure analysis method and system according to the embodiment of the present invention. FIG. 9A is a map of circuit blocks in the semiconductor wafer displayed by the failure analysis method and system according to the embodiment of the present invention, and FIG. 9B is a map of circuit blocks in the semiconductor device. FIG. 10 is a graph showing the defect contribution ratio for each layer constituting the semiconductor device required in the defect analysis method and system according to the embodiment of the present invention. FIG. 11 is a map showing a first example of a system failure among test data acquired in the failure analysis method and system according to the embodiment of the present invention. FIG. 12 is a map showing a second example of system failure in the test data acquired in the failure analysis method and system according to the embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Computer 1a Keyboard 1b Mouse 1c Display 1d Printer 2 Network 3-7 Memory | storage device 11 Semiconductor wafer 12 Semiconductor device 13a-13f Circuit block 13x Rectangular area

Claims (5)

Obtaining from the database design data including area data indicating positions of circuit blocks in a semiconductor device formed on a wafer and data of layers constituting the circuit blocks;
Obtaining shipment test data including test item data in a shipment test performed on the semiconductor device from the database;
Obtaining manufacturing process test data including layer test data of the layer performed in the manufacturing process of the semiconductor device from the database;
Creating a test area table associating the design data of the circuit block, the shipping test data, and the manufacturing process test data;
A step of comparing the circuit block corresponding to the defective portion by the shipping test with a defective portion of the manufacturing process test data;
Displaying on the output unit data based on the test area table of the area where the defective part and the defective part overlap;
A failure analysis method for a semiconductor device, comprising: The writing process to the test area table includes:
Writing the area data of the circuit block that is the subject of the shipping test among the shipping test data;
Writing the test item data for the circuit block;
Writing the layer test data of the circuit block;
The semiconductor device failure analysis method according to claim 1, wherein: A step of acquiring layer data based on a process test result in a manufacturing process from a database of a storage unit for a plurality of layers constituting a circuit block in a semiconductor device formed on a plurality of wafers;
Calculating a defect contribution ratio indicating a contribution ratio of defect occurrence of the circuit block for each of the plurality of layers in the layer data;
Obtaining a defect occurrence rate for each of the circuit blocks in the semiconductor device from a shipment test result database in the storage unit in which test data for shipping the wafer stored in the storage unit is stored;
For each of the plurality of layers, integrating the defect contribution rate to the defect occurrence rate to obtain an integrated value, calculating a sum of the integrated values for each layer, and outputting a calculation result to an output unit;
A failure analysis method for a semiconductor device, comprising: A first storage unit for storing area data indicating positions of circuit blocks in a semiconductor device formed on a plurality of wafers and design data including data of layers constituting the circuit blocks;
A second storage unit that stores shipping test data including test item data in a shipping test performed on the semiconductor device;
A third storage unit for storing manufacturing process test data including layer test data of the layer acquired in the manufacturing process of the semiconductor device;
A data processing unit that creates a test area table that associates the design data of the circuit block, the shipping test data, and the manufacturing process test data;
By comparing the defective portion of the circuit block included in the shipping test data with the defective portion of the circuit block included in the manufacturing process test data, the test region table of the region where the defective portion and the defective portion overlap is compared. A comparison processing unit for selecting data based on;
An output unit for displaying a comparison result by the comparison processing unit;
A failure analysis system for a semiconductor device, comprising: The data processing unit acquires, from the first storage unit, the area data of the circuit block that is the object of the shipping test from the shipping test data, writes the area data in the test area table, and the test for the circuit block Item data is acquired from the second storage unit and written to the test region table, the layer test data of the circuit block is acquired from the third storage unit and written to the test region table,
5. The semiconductor device failure analysis system according to claim 4, wherein the comparison processing unit compares the defective portion with the defective portion for each test item data of the circuit block.

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