KR950003970A - Fast multiplication circuit - Google Patents

Fast multiplication circuit Download PDF

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Publication number
KR950003970A
KR950003970A KR1019930014868A KR930014868A KR950003970A KR 950003970 A KR950003970 A KR 950003970A KR 1019930014868 A KR1019930014868 A KR 1019930014868A KR 930014868 A KR930014868 A KR 930014868A KR 950003970 A KR950003970 A KR 950003970A
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South Korea
Prior art keywords
multiplier
bit
multiplying
partial product
register
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KR1019930014868A
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Korean (ko)
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KR950012088B1 (en
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김성정
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배순훈
대우전자 주식회사
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/487—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/496—Multiplying; Dividing

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Complex Calculations (AREA)

Abstract

본 발명은 승수의 최하위 비트와 최상위 비트를 동시에 피승수에 곱하여 고속 승산을 수행하는 고속 승산 회로에 관한 것이다.The present invention relates to a fast multiplication circuit for performing a fast multiplication by multiplying the least significant bit and the most significant bit of a multiplier by a multiplicand simultaneously.

이와 같은 본 발명은 피승수와 승수의 부분곱을 생성하는 부분곱 생성부(203)와, 가산기(209) 및 쉬프트 레지스터(207) 및 (208)로 구성되어, M비트의 피승수에 N비트의 승수를 승산할 경우, 피승수에 승수의 최하위 비트(LSB)부터 (N/2)비트까지와, 최상위 비트(MSB)부터 (N/2+1) 비트까지의 승산을 병렬 처리함으로써, 승산 단계를 1/2로 줄여 승산 속도를 높인다.The present invention is composed of a partial product generation unit 203 for generating a partial product of a multiplier and a multiplier, and an adder 209, shift registers 207, and 208, and multiplies N bits by a multiplier of M bits. When multiplying, multiplying the multiplicative step by multiplying the multiplier by the least significant bit (LSB) to (N / 2) bits of the multiplier and the most significant bit (MSB) to (N / 2 + 1) bits in parallel. Reduce to 2 to speed up the odds.

또한, 자리수를 맞추기 위하여 자리 이동을 할 때 레지스터를 하나 더 사용하는 대신에 자리수만큼을 그라운드로 처리함으로써, 소자의 수를 줄일 수 있으며, 자리수만큼 그라운드 처리 할 경우, 레지스터 두개를 연결하여 사용할때 보다, 처리 단계마다 1주기씩의 클럭 신호가 감소하기 때문에 고속으로 승산할 수가 있다.In addition, the number of devices can be reduced by processing as many digits as ground instead of using one more register when shifting digits to match the number of digits. Therefore, since the clock signal decreases by one period for each processing step, it can multiply at high speed.

Description

고속 승산 회로Fast multiplication circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 고속 승산 회로를 간략하게 나타낸 블럭도, 제3도는 제2도의 부분곱 생성부의 상세 블럭도, 제4도는 제2도의 하위 비트 승산부의 상세 블럭도.2 is a block diagram schematically showing a fast multiplication circuit according to the present invention, FIG. 3 is a detailed block diagram of a partial product generation unit of FIG. 2, and FIG. 4 is a detailed block diagram of a lower bit multiplication unit of FIG.

Claims (3)

승수의 최하위 비트(LSB)와 최상 비트(MSB)를 동시에 병렬로 피승수에 승산하는 회로에 있어서, M비트(M은 0이 아닌 정수) 피승수가 입력되는 제1레지스터(201)와; N비트(N은 0이 아닌 정수) 승수가 입력되는 제2레지스터(202)와; 상기 제1레지스터(201)에 입력되는 피승수와 모든 비트와 상기 제2레지스터(202)에 입력되는 승수의 각 비트를 승산하여 부분곱을 생성하는 부분곱 생성수단(203)과; 상기 피승수에 승수의 1비트씩 승산한 후, 그 부분곱을 쉬프트 레지스터를 이용하여 우측으로 자리 이동을 한 후 그 값과, 피승수에 승수의 다음 1비트를 승산하여 얻은 부분곱을 가산하여 우측으로 자리 이동하는 과정을 상기 부분곱 생성 수단(202)의 하위 비트에 대해 반복 수행하는 하위 비트 승산 수단(205)과; 상기 피승수에 승수의 1비트씩 승산한 후 그 부분곱을 쉬프트 레지스터를 이용하여 좌측으로 자리이동을 한 후, 그 값과 피승수에 승수의 다음 1비트를 승산하여 얻은 부분곱을 가산하여 좌측으로 자리 이동하는 과정을 상기 부분곱 생성 수단(202)의 상위 비트에 대해 반복 수행하는 상위 비트 승산 수단(206)과; 상기 하위 비트 승산 수단(205)과 상위 비트 승산 수단(206)의 차이나는 자리수를 자리 이동에 의해 맞추는 레지스터(207) 및 (208)와; 상기 레지스터(207) 및 (208)에 의해 자리수가 맞춰진 하위 비트 승산 수단(205)의 출력과, 상위 비트 승산 수단(206)의 출력을 가산하여 출력하는 가산수단(209)을 포함하는 고속 승산 회로.A circuit for multiplying the least significant bit (LSB) and the most significant bit (MSB) of a multiplier at the same time in parallel with a multiplier, comprising: a first register 201 to which an M bit (M is a nonzero integer) multiplier is input; A second register 202 to which an N-bit (N is a non-zero integer) multiplier is input; Partial product generation means (203) for generating a partial product by multiplying a multiplier multiplied by the first register (201) with all the bits and each bit of the multiplier (2) input to the second register (202); After multiplying the multiplicator by one bit of the multiplier, the partial product is shifted to the right using a shift register, and then the value is multiplied by the next multiplier obtained by multiplying the next one bit of the multiplier and shifted to the right. A low bit multiplication means (205) for repeating the steps of performing the process of repeating the low bit of the partial product generating means (202); After multiplying the multiplier by one bit and multiplying the partial product to the left using a shift register, the partial product obtained by multiplying the value and the multiplicand by the next 1 bit of the multiplier is shifted to the left. Higher bit multiplication means (206) for repeating the process for the upper bits of the partial product generating means (202); Registers (207) and (208) for shifting the number of digits that differ between the lower bit multiplication means (205) and the higher bit multiplication means (206) by shifting positions; A high speed multiplication circuit comprising an output of the lower bit multiplication means 205 whose digits are matched by the registers 207 and 208 and an adding means 209 for adding and outputting the output of the upper bit multiplication means 206. . 제1항에 있어서, 상기 제1 및 제2레지스터(201) 및 (202)로 데이타가 연속적으로 입력되는 경우, 최종 출력값들은 승수의 비트수를 2로 나눈 소정 갯수의 클럭 신호가 지난 후, 연속적으로 출력됨을 특징으로 하는 고속 승산 회로.The method of claim 1, wherein when data is continuously input to the first and second registers 201 and 202, the final output values are continuously obtained after a predetermined number of clock signals obtained by dividing the number of bits of the multiplier by two. A high speed multiplication circuit characterized in that the output. 제1항에 있어서, 상기 쉬프트 레지스터(207) 및 (208)는, 일반 레지스터에 자리 이동수만큼의 그라운드(GND)로 처리하여 자리이동하는 레지스터로 사용됨을 특징으로 하는 고속 승산 회로.The high-speed multiplication circuit according to claim 1, wherein the shift registers (207) and (208) are used as registers which are processed by the ground (GND) as much as the number of place shifts in the general register. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930014868A 1993-07-31 1993-07-31 High speed multiplicating circuit KR950012088B1 (en)

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Application Number Priority Date Filing Date Title
KR1019930014868A KR950012088B1 (en) 1993-07-31 1993-07-31 High speed multiplicating circuit

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KR950003970A true KR950003970A (en) 1995-02-17
KR950012088B1 KR950012088B1 (en) 1995-10-13

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