KR950002373A

KR950002373A - Digital zooming circuit

Info

Publication number: KR950002373A
Application number: KR1019930010350A
Authority: KR
Inventors: 천인서
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1993-06-08
Filing date: 1993-06-08
Publication date: 1995-01-04

Abstract

본 발명은 디지탈논리회로를 이용한 디지탈 주밍회로를 공개한다. 그 회로는 하나의 프레임에 해당하는 화소 데이타를 저장하기 위한 화소 데이타 저장메모리, 상기 화소 데이타 저장메모리의 데이타를 그대로 저장하거나 상기 화소 데이타 저장메모리의 확대를 원하는 어드레스부터의 화소 데이타를 소정배수로 증가하여 디스프레이를 위한 하나의 프레임에 해당하는 화소 데이타를 저장하기 위한 디스플레이 화소 데이타 저장메모리, 상기 화소 데이타 저장메모리와 상기 디스플레이 화소 데이타 저장메모리에 화소 데이타를 저장하기 위한 어드레스를 발생하기 위한 라이트 어드레스 발생수단, 상기 화소 데이타 저장메모리와 상기 디스플레이 화소 데이타 제장메모리로 부터 화소 데이타를 독출하기 위한 어드레스를 발생하기 위한 리드 어드레스 발생수단으로 구성되어 있다. 따라서, 디지탈 주밍을 간단하게 구현할 수 있다.The present invention discloses a digital zooming circuit using a digital logic circuit. The circuit stores a pixel data storage memory for storing pixel data corresponding to one frame, and stores the data of the pixel data storage memory as it is or increases the pixel data from an address desired to enlarge the pixel data storage memory by a predetermined multiple. A display pixel data storage memory for storing pixel data corresponding to one frame for display, write address generating means for generating an address for storing pixel data in the pixel data storage memory and the display pixel data storage memory; And read address generating means for generating an address for reading pixel data from the pixel data storage memory and the display pixel data storage memory. Therefore, digital zooming can be easily implemented.

Description

Digital zooming circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 디지탈 주밍회로의 블럭도, 제2A~C도는 메모리에 저장된 데이타의 상태를 나타내는 것.1 is a block diagram of a digital zooming circuit of the present invention, and FIGS. 2A to C are diagrams showing the state of data stored in a memory.

Claims

A pixel data storage memory for storing pixel data corresponding to one frame; Display pixel data storage memory for storing pixel data corresponding to one frame for display by storing the data of the pixel data storage memory as it is or increasing the pixel data from an address for which the pixel data storage memory is desired to be enlarged by a predetermined multiple. ; Write address generating means for generating an address for storing pixel data in the pixel data storage memory and the display pixel data storage memory; And a read address generating means for generating an address for reading pixel data from said pixel data storage memory and said display pixel data storage memory.

2. The first counting means according to claim 1, wherein the write address generating means uses a signal divided by two of the vertical synchronization clocks as the highest horizontal light address, and the pixel clock responds to generate a horizontal light address and is cleared in response to the horizontal synchronization clock. ; And second counting means for generating a vertical write address in response to the horizontal synchronous clock and clearing in response to the vertical synchronous clock.

2. The apparatus of claim 1, wherein the read address generating means comprises: first selecting means for selectively outputting a signal divided by two for the pixel clock and a signal divided by four for the pixel clock; Third counting means for generating a horizontal lead address in response to a clock signal selected by said first selecting means and clearing by said horizontal synchronous clock; Second selection means for selectively outputting a signal obtained by dividing the horizontal synchronization clock and the horizontal synchronization clock by two; Fourth counting means for generating a vertical lead address in response to the clock signal selected by said second selecting means and being cleared by said vertical synchronous clock; Horizontal lead address generating means for generating an actual horizontal lead address by adding an output address of the third counting means and a designated horizontal offset address; And a digital read address generating means for generating an actual vertical read address by adding the output address of the fourth counting means and the designated vertical offset address.

2. The apparatus of claim 1, wherein the pixel data storage memory and the display pixel data storage memory further comprise: third selection means for selectively outputting addresses from the write address generating means and the read address generating means; Fourth selecting means for selectively outputting the write address and the address from the read address generating means; A first memory for storing or reading pixel data in response to an output address of the third selecting means; A second memory for storing or reading pixel data in response to an address of an output of said fourth selecting means; And fifth selecting means for selectively outputting output data of the first memory and the second memory.

※ Note: The disclosure is based on the initial application.