KR950000442B1 - Apparatus for saving the capacity of memory devices for time base correction of vcr - Google Patents

Abstract

The memory capacity saving apparatus comprises a Y/C separator, a clamp part, an A/D converter, a memory, a D/A converter, a sync separator, a clock generator, a write control part, a read control part, a color auto gain adjuster, a frequency converter, an adder, a vertical initializing pulse generator, and an oscillator, a sync generator. A read control signal is positioned at the center part of a write control signal on each field, such that the memory capacity for time base correction in VTR is saved.

Description

Memory savings in VT's time base collection

1 is a block diagram of a time base collection apparatus of the conventional VTIAL.

2A to 2F are timing diagrams of a conventional memory control.

3 is a block diagram of the time base collection apparatus of the present invention VTI.

4A to 4H are timing diagrams of the memory control of the present invention.

* Explanation of symbols for main parts of the drawings

1: luminance / color separation unit 2: clapping unit

3, 11: A / D converter 4, 12: memory

5, 13: D / A converter 6: Synchronous separator

7: Clock generator 8: Light control unit

9: Lead control roll 10: Color automatic gain adjustment

14: frequency converter 15: vertical initialization pulse generator

16: synchronization generator 17: oscillator

The present invention relates to Time Base Correction (TBC) of VTRs. In particular, the present invention relates to a method in which a memory having a large capacity is used even though a small memory is used in the TBC. A memory capacity saver in the time base collection of a Thial.

FIG. 1 is a block diagram of a conventional VT-based time base collection device. As shown in FIG. 1, a luminance / color separation unit 1 for separating a reproduced signal into color (C) and luminance (Y) signals, and A clamping unit 2 for keeping the level of the separated luminance signal Y constant, an A / D conversion unit 3 for converting the clamping level signal into a digital signal with the light clock signal WCLK, and digital conversion data. A memory 4 stored by the write clock signal WCLK and the write control signal WRST and read by the read control signal RRST and the read clock signal RCLK, and the memory by the read clock signal RCLK. A D / A converter (5) for converting the digital data of (4) into an analog signal, a color automatic gain adjusting unit (10) for automatically adjusting the gain of the color signal (C), and the automatic gain output A / D converter 11 for converting digital data into digital data by WCLK, and WCL K), a memory 12 that stores data of the A / D converter 11 by a write control signal WRST and reads it by a read clock signal RCLK and a read control signal RRST, and the memory A frequency for converting the digital data of (12) into an analog signal by the read clock signal RCLK and the analog signal of the D / A converter 13 into a 3.58 MHz frequency. A converter 14, a synthesizer A1 for synthesizing and outputting the output of the frequency converter 14 and the output of the D / A converter 5, and a synchronous separation for separating synchronization from the clamped signal. The clock generator 7 for generating a clock CLK locked to the separated horizontal sync signal H.SYNC, and to the horizontal sync signal H.SYNC and the clock CLK. The light control section 8 which generates the write signal WCLK and the write control signal WRST, and the read clock signal RCLK and read control signal by the reference synchronization signal and the reference clock signal. The description will be given with reference to FIGS. 2 (a)-(f), which are timing diagrams, which are composed of the lead control section 9 generating RRST.

After the luminance / color separation unit 1 separates the luminance signal Y and the color signal C, the clamping unit 2 clamps the reference level so that the reference level does not change according to the brightness and darkness of the luminance Y. The synchronization separator 6 receiving the signal separates the horizontal synchronization signal H. SYNC as shown in FIG.

At this time, when the clock generator 7 generates a clock CLK synchronized with the horizontal synchronization H. SYNC, the light control unit 8 generates the second control signal based on the horizontal synchronization signal H.SYNC and the clock signal. A light control signal WRST is generated as shown in c). The write control signal WRST should not exceed the capacity of the memory 4 at the point where it falls from the high potential of the write control signal WRST to the low potential.

On the other hand, since the period of the horizontal synchronization signal H.SYNC is not constant, the reproduction clock signal WCLK also changes in accordance with the horizontal synchronization signal H.SYNC, as shown in FIG. When the A / D converter 3 converts the luminance signal Y, which has a constant level, to the digital data by the light clock WCLK, the light clock signal WCLK and the light control signal WRST. Is stored in the memory 4.

In this way, the data stored in the memory 4 is read by the read clock signal RCLK and read control signal RRST generated by the read control unit 9 as shown in FIG. 2 (e) (f). In order to maximize the capacity of the memory 4, the read control signal RRST and the read clock signal RCLK are output at a constant clock. Here, the read control signal RRST and the read clock signal RCLK are generated by the reference control signal 9 and the reference clock signal as shown in FIG.

At this time, as the D / A converter 5 converts the output data of the memory 4 into an analog signal by the read clock signal RCLK, a video luminance signal having a constant period of the horizontal sync signal H.SYNC is generated. Is made.

In addition, the color signal C is also processed through the color automatic gain adjusting unit 10, the A / D converter 11, the memory 12, and the D / A converter 13 as described above, and then the frequency converter ( Convert the 629KHz signal to 3.58MHz.

In this way, a stable screen can be obtained by synthesizing the color signal C and the luminance signal Y through the combining unit A1. However, in the conventional time base collection apparatus as described above, the change of the video signal to be reproduced must be minute. That is, since the read control signal is a constant period and the write control signal changes according to the reproduced signal, the write control signal and the read control signal should not coincide with each other. To do this, the change of the write control signal is ± 1 of the read control signal period. Must be in the range of / 2.

Therefore, when the read control signal and the write control signal cross each other, the data to be written and the data to be read are different from each other. Therefore, the accuracy of the system or the large capacity of the memory is required so that they do not coincide with each other. There is a need for a device to control the problem, which makes it difficult to realize.

An object of the present invention is to solve the above-mentioned problems, even if the memory capacity is small without configuring a highly precise system, the read control signal and the read control signal is placed in the center of the light control signal every field. A memory saving device was created at the time base collection of VTIAL to prevent control signals from intersecting with each other, which will be described in detail with reference to the accompanying drawings.

3 is a block diagram of the time base collection apparatus of the present invention VTIAL, as shown therein, the luminance / color separation unit 1, the clamping unit 2, the A / D conversion unit 3, 11, Memory (4) (12), D / A Converter (5) (13), Synchronous Separation (6), Clock Generator (7), Light Control (8), Lead Control (9), Color Auto In the conventional time base collection apparatus comprising the gain adjusting section 10, the frequency converter section 14, and the combining section A1, the synchronization separating section 6 is arranged in accordance with the clock CLK of the clock generating section 7. A vertical initialization pulse generator 15 for generating a vertical initialization pulse Vint by calculating a horizontal synchronization signal H.SYNC and an odd / even signal PB O / E, and an oscillator for oscillating a clock of a predetermined frequency ( 17) and a vertical initialization pulse Vint is generated in synchronization with the output REF CLK of the oscillation unit 17, and at the same time, a horizontal synchronization signal REF H. SYNC is output to the read control unit 9, and the horizontal Sync signal (REF H. S When the 3H period elapses after the YNC), the synchronization controller 16 outputs the oven / even discrimination signal REF O / E to the lead control unit 9.

The odd / even signal PB O / E is a playback signal.

The light control unit 8 outputs the light clock signal WCLK according to the horizontal synchronization signal H. SYNC, and also outputs the light control signal WRST for every 3H horizontal synchronization signal H. SYNC.

The lead control unit 9 generates a read clock signal RCLK according to the output REF CLK of the oscillation unit 17 and generates an odd / even discrimination signal REF O / E of the synchronization generator 16. At the same time, after generating the read control signal RRST, the read control signal RRST is generated every 3H of the horizontal synchronization signal REF H. SYNC.

4A to 4H are timing charts of the memory control of the present invention, as shown in FIG.

Hereinafter, the operation and effect of the present invention configured as described above will be described.

First, luminance / color separation unit 1, clamping unit 2, A / D conversion unit 3, 11, memory 4, 12, D / A conversion unit 5, 13, synchronization The operations of the separation unit 6, clock generation unit 7, color automatic gain adjustment unit 10, light control unit 8, lead control unit 9, and frequency converter A1 are the same as in the prior art.

In this case, the clamping unit 2 for maintaining the luminance signal Y of the luminance / color separation unit 1 separating the luminance Y and the color C signals from the video signal as shown in FIG. The synchronizing separator 6 receiving the output of the < RTI ID = 0.0 > (6) < / RTI > separates the horizontal synchronizing signal H.SYNC as shown in FIG. The clock generator 7 then generates a synchronization clock CLK to the horizontal synchronization signal H.SYNC.

Accordingly, the light controller 8 transmits the light clock signal WCLK to the A / D converters 3, 11 and the memory 4, 12 according to the clock CLK of the clock generator 7. Each time the horizontal synchronization signal H.SYNC of the synchronization separator 6 is counted by 3H, the write control signal WRST is output to the memories 4 and 12 as shown in FIG. .

Here, the write control signal WRST is generated at the same time as the video reproduction signal as shown in FIG. 4 (a) becomes the odd field, and is subsequently generated every 3H of the horizontal synchronization signal H. SYNC.

The vertical initialization pulse generator 15 counts the horizontal sync signal H.SYNC of the sync separator 6 to 260H, and then counts the clock CLK of the clock generator 7 by 0.5H. As shown in (e), a vertical initialization pulse Vint is generated.

That is, the vertical initialization pulse generator 15 counts the horizontal synchronizing signal H.SYNC as shown in FIG. 4 (c) to 260H, counts the clock CLK by 0.5H, and becomes 26.5H. Before 1.5H, the vertical initialization pulse Vint is generated.

At this time, the synchronization generator 16 synchronized with the clock REF CLK of the oscillator 17 generates a vertical initialization pulse Vint and simultaneously generates the horizontal synchronization signal REF H. SYNC as shown in FIG. Is generated, and the horizontal synchronization signal H. SYNC is counted by 3H, and the odd / even discrimination signal REF O / E is output to the read control unit 9 as shown in FIG.

Here, an odd / even discrimination signal REF O / E is generated as shown in FIG. 4F after 3H period after the vertical initialization pulse Vint as shown in FIG. 4E. This is for synchronizing since the period of the vertical synchronizing signal is 3H.

Accordingly, the read control unit 9 outputs the read clock RCLK to the memory 4 and the D / A converter 5 and 13 in synchronization with the clock REF CLK of the oscillator 17. Read control to the memory 4 and 12 as shown in FIG. 4 (h) in accordance with the horizontal synchronizing signal REF H. SYNC and the odd / even discrimination signal REF O / E of the synchronization generating unit 16. The signal RRST is outputted.

At this time, the read controller 9 generates the read control signal RRST at the same time as the odd / even discrimination signal REF O / E is generated by the sync generator 16 and then the horizontal sync signal REF H. SYNC. ) Is generated every time the 3H count is continued to generate the read control signal RRST.

Here, the read control signal RRST is centered in the write control signal WRST so that the vertical initialization pulse Vint is shown in FIG. 4A as shown in FIG. 4E. Occurs before 1.5H of the odd field of the video reproduction signal.

The capacity of the memories 4 and 12 is such that only 3H of the video reproduction signal can be stored.

Therefore, the read control signal RRST comes in the middle of the write control signal WRST every one frame so that the write control signal WRST and the read control signal RRST even if the capacity of the memory 4 or 12 is only 3H. ) Do not cross each other.

Accordingly, a write operation of the memory 4 and 12 is performed according to the write clock signal WCLK and the write control signal WRST and a read operation is performed according to the read clock signal RCLK and the read control signal RRST. Therefore, one screen is composed of one frame of the video signal.

Here, one frame of the video signal is divided into an odd field and an even field, and the variation range of the video reproduction signal is very small, less than 1H during one frame period.

When the vertical initialization pulse Vint is generated every frame, the data is corrupted at the position where the vertical initialization pulse Vint is generated. This is a minute amount of data that is not visible on the screen. It doesn't work.

As described in detail above, the present invention prevents the read control signal from being intersected by placing the read control signal in the center of the write control signal in every field even if the memory capacity is small. The same effect can be achieved.

Claims (5)

The reproduction signal is separated from the horizontal synchronizing signal 1 into the luminance signal Y and the color signal C to automatically adjust the gain of the color signal C, and clamp the luminance signal Y to a predetermined level, respectively. Signal is converted into digital by the A / D converter (3) (11) according to the light clock (WCLK) and is respectively stored in the memory (4) (12) in accordance with the light clock signal (WCLK) and the light control signal (WRST). In response to the read clock signal RCLK and the read control signal RRST, the signal output from the memory 4 and 12 is converted by the D / A converter 5 and 13 according to the read clock signal RCLK. After the analog conversion, the frequency converter 14 converts the output frequency of the D / A converter 13, and then, in the synthesizer A1, the output of the frequency converter 14 and the D / A converter 5 A VTI configured to synthesize an output, comprising: separating a horizontal sync signal (H. SYNC) and an odd / even signal (PB O / E) from a signal clamped with a luminance signal (Y) The clock generator 7, which generates a clock CLK based on the horizontal synchronization signal H. SYNC of the synchronization separator 6, and the clock generator 7 The light clock signal WCLK is output according to the clock CLK, and the light control signal WRST is calculated by calculating the odd / even signal PB O / E and the horizontal synchronization signal H. SYNC of the synchronization separator 6. ) Is calculated by calculating the output (H.SYNC) (PB O / E) of the synchronization separator (6) according to the light control unit (8) for outputting the clock controller (7) and the clock (CLK) of the clock generator (7). The vertical initialization pulse generator Vint generating the initialization pulse Vint, the oscillation unit 17 generating the clock of a constant frequency, and the vertical initialization pulse Vint in synchronization with the output REF CLK of the oscillation unit 17. Is generated at the same time as generating a horizontal synchronization signal (REFH. SYNC) and then generates an odd / even discrimination signal (REF O / E), and an output (REF CLK) of the oscillator (17). Lead clock A read control that outputs a call RCLK, calculates an odd / even discrimination signal REF O / E and a horizontal sync signal REF H.SYNC of the sync generator 1, and outputs a read control signal RRST. A memory saver for time base collection of VPials, comprising a section (9). The apparatus of claim 1, wherein the vertical initialization pulse generator (15) generates a vertical initialization pulse (Vint) before 1.5H of the odd field. The light control unit 6 becomes an odd field and outputs the light control signal WRST, and then writes the light control signal every 3H of the horizontal synchronization signal H.SYNC of the synchronization separation unit 6. WRST), and outputs a memory saving device for the time base collection of VP. 2. The synchronization generator 16 generates the horizontal synchronization signal REF H.SYNC simultaneously with the generation of the vertical initialization pulse Vint, and generates the signal after 3H of the horizontal synchronization signal REF H.SYNC. And a time-saving collection of VTIAL, characterized by outputting a / even discrimination signal (REF O / E). The read control unit 9 becomes the odd field and simultaneously outputs the read control signal RRST. Then, read control is performed every 3H of the horizontal synchronization signal REF H.SYNC of the synchronization generating unit 16. A memory saving apparatus for time base collection of VTial, characterized by continuously outputting a signal RRST.