KR950000410Y1 - Flip chip testing apparatus - Google Patents
Flip chip testing apparatus Download PDFInfo
- Publication number
- KR950000410Y1 KR950000410Y1 KR2019910017062U KR910017062U KR950000410Y1 KR 950000410 Y1 KR950000410 Y1 KR 950000410Y1 KR 2019910017062 U KR2019910017062 U KR 2019910017062U KR 910017062 U KR910017062 U KR 910017062U KR 950000410 Y1 KR950000410 Y1 KR 950000410Y1
- Authority
- KR
- South Korea
- Prior art keywords
- flip chip
- pcb
- insulating film
- bumps
- testing apparatus
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본고안 장치의 요부인 절연 필름의 정면도.1 is a front view of an insulating film that is a main part of the present invention device.
제2도는 플립칩에 절연 필름을 부착하여 테스팅하는 상태를 나타낸 일부 종단면도.2 is a partial longitudinal sectional view showing a state in which an insulating film is attached to a flip chip for testing.
제3도는 본고안 장치의 사시도.3 is a perspective view of the present design device.
제4도는 제3도의 일부를 나타낸 정면도.4 is a front view showing a part of FIG.
제5도는 종래 플립칩을 나타낸 단면도.Figure 5 is a cross-sectional view showing a conventional flip chip.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 플립칩 2 : 범프1: flip chip 2: bump
3 : 절연 필름 4 : 필름 호울3: insulation film 4: film hole
6 : 테스트 패턴 7 : PCB6: test pattern 7: PCB
본고안은 플립칩(Filp Chip)을 PCB상에 장착하기 전에 불량유무를 테스트하기 적당하도록 된 플립칩의 테스팅장치에 관한 것이다.This paper relates to a flip chip testing apparatus adapted to test for defects before mounting a flip chip on a PCB.
종래에는 플립칩을 PCB 기관에 고정시키기 위해 제5도에 도시한바와 같이 플립칩(1)상에 범프(2)를 형성하여 다이싱(Dicing)한후 페이스 다눙하여 칩전극의 범프(2)와 PCB(7)의 패턴위치를 일치시켜 본딩하도록 되어 있다.Conventionally, in order to fix the flip chip to the PCB engine, as shown in FIG. 5, bumps 2 are formed on the flip chip 1 by dicing, followed by face bumps and bumps 2 of the chip electrodes. The pattern position of the PCB 7 is matched and bonded.
따라서 플립칩을 PCB(7)상에 본딩시킨 상태에서만 디바이스의 동작요부를 확인하는 테스트가 가능하기 때문에 만약 불량인 경우는 PCB(7)상에 본딩된 플립칩(1)을 제거하고 새로운 플립칩을 본딩한 후 전술한 바와 같이 동작여부를 테스트해야 되는 번거로운 결점이 있었다.Therefore, it is possible to test the operation of the device only when the flip chip is bonded on the PCB (7). In case of failure, remove the flip chip (1) bonded on the PCB (7) and replace the new flip chip. After bonding, there was a cumbersome drawback to test the operation as described above.
본고안은 종래의 이와같은 결점을 감안하여 안출한 것으로서, 플립칩을 PCB상에 본딩하기 전에 테스트를 실시할 수 있도록 하여 양품의 플립칩만을 PCB에 본딩할 수 있도록 하는데 그 목적이 있다.The present invention has been made in view of the above-described drawbacks of the prior art, and its purpose is to enable the test to be conducted before bonding the flip chip onto the PCB so that only good flip chips can be bonded to the PCB.
상기 목적을 달성하기 위한 본고안 형태에 따르면, 플립칩에 범프를 형성하여 PCB상에 본딩하도록 된것에 있어서, 플립칩에 테스트 패턴과 필름호울이 형성된 절연 필름을 부착하여 플립칩을 PCB상에 본딩하기전에 테스팅할 수 있도록 플립칩의 테스팅 장치가 제공된다.According to the present invention for achieving the above object, the bump is formed on the flip chip to bond on the PCB, the flip chip is bonded on the PCB by attaching an insulating film formed with a test pattern and a film hole on the flip chip A flip chip testing apparatus is provided for testing prior to doing so.
이하, 본고안을 일실시예로 도시한 첨부된 도면 제1도 내지 제4도를 참고로 더욱 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in more detail with reference to FIGS. 1 to 4 of the accompanying drawings showing an embodiment as follows.
첨부도면 제1도는 본고안 장치의 요부인 절연 필름의 정면도이고 제2도는 플립칩에 절연 필름을 부착하여 테스팅하는 상태를 나타낸 일부 종단면도로서, 플립칩(1)에 형성된 패턴에 범프(2)가 형성되어 있고 판상으로 된 절연필름(3)에는 플립칩(1)에 형성된 범프(2)와 동일한 위치에 필름 호울(4)이 형성되어 있으며 필름 호울(4)에는 플로브팁(5)에 의해 플립칩(1)을 테스트하기 위한 테스트 패턴(6)이 형성되어 있다.1 is a front view of an insulating film, which is a main part of the present device, and FIG. 2 is a partial longitudinal cross-sectional view showing a state in which an insulating film is attached and tested on a flip chip, and bumps 2 are formed on a pattern formed on the flip chip 1. Is formed and the plate-shaped insulating film 3 has a film hole 4 formed at the same position as the bump 2 formed on the flip chip 1, and the film hole 4 has a flop tip 5 formed thereon. As a result, a test pattern 6 for testing the flip chip 1 is formed.
따라서 프립칩(1)을 PCB(7)상에 형성된 범프(8)와 고정하기전에 플립칩(1)에 형성된 범프(2)를 절연 필름(3)의 필름 호울(4)과 일치되도록 하여 상호 고정시킨다.Therefore, the bumps 2 formed on the flip chip 1 are aligned with the film holes 4 of the insulating film 3 before fixing the flip chip 1 to the bumps 8 formed on the PCB 7. Fix it.
이와같이 플립칩(1)에 절연필름(3)을 고정시킨 후 제2도에 도시한 바와 같이 플립칩(1)을 테스트하기위한 플로브팁(5)을 절연 필름(3)에 형성된 테스트 패턴(6)과 접속시킴으로써 플립칩(1)의 테스트가 가능해지게 된다.After fixing the insulating film 3 to the flip chip 1 as described in FIG. 2, the test pattern formed on the insulating film 3 includes a plov tip 5 for testing the flip chip 1. 6), the flip chip 1 can be tested.
상기한 바와같은 테스트에 의해 플립칩(1)이 양품일 경우에는 절연필름(3)의 테스트 패턴(6)을 PCB(8)상의 범프(8)와 일치시켜 상호 고정시킴으로써 고정부에 2중 범프가 형성되는 것이다.When the flip chip 1 is a good product by the test as described above, the double bumps are fixed to the fixing part by fixing the test pattern 6 of the insulating film 3 to the bumps 8 on the PCB 8 and mutually fixing them. Is formed.
이상에서와 같이 본고안은 필름호울(4)과 테스트 패턴(6)이 형성된 절연 필름(3)을 이용하여 플립칩(1)을 PCB상에 고정시키기전에 테스트 할 수 있게 되므로 불량품의 고정으로 인한 불필요한 시간을 줄일 수 있게 됨은 물론 2중 범프의 형성으로 인해 페이스 다운시 플립칩(1)에 작용하는 열을 차단시켜 열로 부터 플립칩(1)을 보호할 수 있게 되는 효과를 가지게 된다.As described above, this proposal can be tested before fixing the flip chip 1 on the PCB by using the insulating film 3 on which the film hole 4 and the test pattern 6 are formed. The unnecessary time can be reduced, as well as the formation of the double bumps has the effect of protecting the flip chip 1 from heat by blocking the heat acting on the flip chip 1 during face down.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019910017062U KR950000410Y1 (en) | 1991-10-14 | 1991-10-14 | Flip chip testing apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019910017062U KR950000410Y1 (en) | 1991-10-14 | 1991-10-14 | Flip chip testing apparatus |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930009351U KR930009351U (en) | 1993-05-26 |
KR950000410Y1 true KR950000410Y1 (en) | 1995-01-25 |
Family
ID=19320541
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR2019910017062U KR950000410Y1 (en) | 1991-10-14 | 1991-10-14 | Flip chip testing apparatus |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR950000410Y1 (en) |
-
1991
- 1991-10-14 KR KR2019910017062U patent/KR950000410Y1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR930009351U (en) | 1993-05-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR960013779B1 (en) | Semiconductor package for flip-chip mounting process | |
KR930022510A (en) | Method of manufacturing a semiconductor device having only test contacts | |
US6061248A (en) | Semiconductor chip-mounting board providing a high bonding strength with a semiconductor chip mounted thereon | |
JP3459765B2 (en) | Mounting inspection system | |
JPH05129366A (en) | Tab mounting structure for integrated circuit use | |
JP2907168B2 (en) | Semiconductor device and bonding structure of semiconductor device and substrate | |
KR920020708A (en) | Fragile links based on wetting | |
KR950000410Y1 (en) | Flip chip testing apparatus | |
JPS6481330A (en) | Film carrier semiconductor device | |
KR19990063444A (en) | Semiconductor devices | |
JPS6412565A (en) | Semiconductor integrated circuit | |
JPH02292851A (en) | Lead frame | |
KR960001421Y1 (en) | Chip for electronics device having test terminal | |
JPH0964238A (en) | Structure and method for mounting semiconductor chip | |
KR920017219A (en) | Semiconductor device and manufacturing method of semiconductor device and tape carrier | |
JPH02271547A (en) | Film carrier-type semiconductor device | |
KR970018435A (en) | Semiconductor Package Mounting Method | |
KR940006872Y1 (en) | Circuit substrate structure of multi chip module | |
JPH01319956A (en) | Semiconductor integrated circuit | |
KR0129925Y1 (en) | Mounting apparatus of chip for surface mounting | |
JPS60759A (en) | Semiconductor element carrier | |
KR970077418A (en) | Manufacturing method of hardened dough using lead frame | |
KR100233556B1 (en) | Reliability test method of semiconductor chip | |
JPH0653373A (en) | Ic carrier and method of testing and mounting ic | |
JPH08146082A (en) | Method and apparatus for testing bare chip |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
E701 | Decision to grant or registration of patent right | ||
REGI | Registration of establishment | ||
FPAY | Annual fee payment |
Payment date: 20021223 Year of fee payment: 9 |
|
LAPS | Lapse due to unpaid annual fee |