KR950000399Y1 - Dual port memory access control circuit of multiprocessor system - Google Patents

Abstract

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Description

Dual Port Memory Access Control Circuit in Multiprocessor System

1 is a block diagram of an embodiment of a dual port memory access control circuit of a multiprocessor system according to the present invention;

2 is a block diagram of another embodiment of a dual port memory access control circuit of a multiprocessor system according to the present invention;

3 is an operational waveform diagram of the present invention.

* Explanation of symbols for main parts of the drawings

G1, G2: Oagate G3, G5: Endgate

G4: Noah Gate FF1-FF5: Deflip-flop

CNT: Counter 100: First Selection Signal Generator

200: second selection signal generator 300: access signal generator

400: control unit

The present invention relates to an access control circuit that prevents mutual collision when accessing the same memory for data transmission and reception between processors in a multiprocessor system, and specifically, a RAM access control circuit dedicated to dual port selection and system interface. It is about.

In general, dual port RAM (DRP) is used to send and receive data quickly in multiprocessor systems. At this time, in order to access the contents of the same memory without conflict with each other, an adjustment circuit is required between the two processors. In the conventional case, a dual port DRAM controller having various additional functions as well as dual port selection function is used. did.

However, the dual port DRAM controller is expensive and inconvenient to use, and also does not have a system interface function by itself.

Accordingly, an object of the present invention is to provide a dedicated DPR access control circuit of a multiprocessor system capable of not only dual port selection but also system interface.

In order to achieve the above object, the present invention provides a dual port memory access control circuit of a multiprocessor system having first and second processors each generating first and second memory request signals to access the same memory. A first clock and a first memory input signal having a predetermined clock and the first and second memory request signals, and having opposite states to select only one of the two signals as valid when the two signals are generated at substantially the same time; And a second selection signal for synchronizing the result of the logical multiplication of the selection unit for generating a selection signal, the memory lead and the write signal, and counting the second selection signal in synchronization with the clock. A first access unit for generating an access signal for the first memory request signal upon detecting an end of the access operation for the first memory request signal, a memory lead, The second memory request signal is input in synchronization with a result of the logical multiplication of the write signal, and the second memory request signal is detected by counting a first selection signal in synchronization with the clock to detect the end of the access operation for the first memory request signal. And a second access unit for generating an access signal for the signal.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In addition, in the following description, many specific details such as specific components of a circuit, logic logic states, and the like appear, which are provided to help a more comprehensive understanding of the present invention, and the present invention may be practiced without these specific details. It will be apparent to those of ordinary skill in the art. And in describing the present invention, if it is determined that the detailed description of the related air function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

FIG. 1 is a dual-port selection portion of the inventive circuit, and includes a first memory request signal (CSI) generated from a microprocessor (not shown) of a host processor board and a 4D flip-flop described below. The first O gate G1 for ORing the signal output from the inverted output terminal of FF4 and the first D flip for latching the first O gate G1 output at the rising edge of the clock CLK generated from the microprocessor. The second selection signal CS2-L, which is connected to the flop FF1 and the non-inverting output terminal of the first D flip-flop FF1, generates a first selection signal CSI-L at the rising edge of the clock CLK. A first selection signal generation unit 100 including a second D flip-flop FF2 set under the control of the second memory device, a second memory request signal CS2 and the second D flip-flop FF2 generated from the microprocessor. ) Is the second or gate G2, OR of the inverted output and The 3D flip-flop FF3 latches the output of the second oar gate G2 at the falling edge of the clock CLK, and the 3D flip-flop FF3 output is latched at the falling edge of the clock CLK. And a second selection signal generator 200 which generates a second selection signal CS2-L and is configured by a fourth D flip-flop FF4 which is set under the control of the first selection signal CSI-L.

FIG. 2 is an interface portion of the inventive circuit connected to FIG. 1 and includes a first gate G3 and a first AND gate for performing an AND operation on the memory leads and the memory write signals MRD and MWR generated from the microprocessor. An access signal generator 300 formed of a 5D flip-flop FF5 for latching the first memory request signal CS1 and generating an access signal Rdy in synchronization with an output of the gate G3, and the fifth flip The counter CNT is cleared under the control of the signal generated from the inverted output terminal of the flop FF5 and counts a predetermined period by using the second selection signal CS2-L as one input. The AND gate G5 and the second AND gate G5 output and the logic of multiplying the signals generated from the first output Q1 and the fourth output Q6 terminals with the second selection signal CS2-L are reset. Set b of the fifth flip-flop FF5 by negative logic of the signal RST. ar) consists of a control unit 400 composed of a noah gate (G4) for controlling the terminal (S).

3 is a waveform diagram according to a circuit operation of the present invention, where (a) is a clock CLK, (b) is a first memory request signal CS1, and (C) is a second memory request signal CS2. (D) is the first selection signal CSI-L, and (e) is the second selection signal CS2-L.

Based on the above configuration, the dual port memory access control operation will be described in detail.

Assuming that different systems in FIG. 1 generate the first and second memory request signals CS1 and CS2 almost simultaneously as shown in FIGS. 3B and 3C to use the memory, FIG. In the falling edge T1 of the clock for arbitration, the first memory request signal CS1 generated from the microprocessor of the host processor board and the inverted output terminal of the 4D flip-flop FF4 are generated. The output of the first or gate G1 for ORing the two selection signals CS2-L is in a " high " state. However, the first D flip-flop FF1 for inputting the output of the first o gate G1 and the second D flip-flop FF2 for inputting the output of the first flip-flop FF1 are rising edges of the clock signal CLK. Since it does not operate at the falling edge T1, the first selection signal generated from the non-inverting output terminal of the 2D flip-flop FF2 is kept high as shown in (d). do. At the point of time T2, the second selection signal CS2-L is in the "low" state, and remains "low" until the point of time T3, and is inverted to the "high" state at the point of time T3. However, at the time T4, since the clock signal CLK is in the rising edge state, the first and second D flip-flops FF2 are operated and the state of the signal inverting the clock signal CLK through the inverter INV1. According to the third and fourth D flip-flops (FF3, FF4) is not operated. Therefore, at the time T4, the first selection signal CSI-L is inverted to the "low" state and the second selection signal CS2-L remains the "high" state. As a result, the circuit of FIG. 1 shows that the first selection signal CS1 -L or the second selection signal CS2 -L when the first or second memory request signals CS1 and CS2 are generated at about the same time. One of the first and second memory request signals CS1 and CS2 is selected by having one of the specific logic states and the other having the opposite logic state.

In reality, when designing a DRP circuit, two circuits of FIG. 2 are attached to and used in FIG. 1, but in the present embodiment, for the sake of convenience, a relationship between signals in which one system accesses a memory in FIG. In FIG. 2, when the first memory request signal CS1 occurs (assuming that the signal level is active low), the second selection is not performed when the memory access state is not performed by the second memory request signal CS2. Since the signal CS2-L is in the "high" state, an access signal is transmitted from the non-inverting output terminal of the fifth flip-flop FF5 to the PC-AT system (not shown) so that the first memory request signal CS1 is immediately accessed. (Rdy) is generated and remains "high" only for one cycle. However, when the memory is being used by the second memory request signal CS2 at the time when the first memory request signal CS1 occurs, the second tag signal CS2-L and the counters CNT first and fourth The output of the second and gate G5, which is the AND product of the outputs, becomes a "low" state. Therefore, the output of the no-gate G4 which logically combines the output of the second and gate G5 and the reset signal RST is " high " to set the set terminal S of the second flip-flop FF2 to " low " "I'll put it in a state. Therefore, the first and gate G3 outputs of the logical AND of the memory write and read signals MRD and MWR are input as clock signals, and the first memory request signal CS1 is input to generate an access signal Rdy. Since the 5D flip-flop FF5 is not set, the access signal Ray in the " low " state is continuously generated. As a result, the first memory request signal CS1 is not accessed. However, when the access of the second memory request signal CS2 is terminated and the second select signal CS2-L becomes “high,” the fifth D flip-flop FF5 is set in the same order as described above. Rdy changes to the "high" state so that the first memory request signal CS1 is accessed.

The present invention as described above has the advantage that can be widely used in the system requiring the DPR access without any restriction, and also can be easy to use and low cost DPR circuit can be easily designed.

Claims (1)

A dual port memory access control circuit of a multiprocessor system having first and second processors for generating first and second memory request signals, respectively, for accessing the same memory, comprising: a predetermined clock and the first and second memories; A selection unit for inputting a memory request signal and generating first and second selection signals having opposite states to select only one of the two signals as valid when the two signals are generated at substantially the same time point; Inputting the first memory request signal in synchronization with a result of logical multiplication of a memory lead and a write signal, counting a second selection signal in synchronization with the clock to detect an end of an access operation for the second memory request signal; Synchronize with a result of logically multiplying the first access unit for generating an access signal for one memory request signal with the memory lead and write signals For example, when the second memory request signal is input and the first selection signal is counted in synchronization with the clock to detect the end of the access operation for the first memory request signal, an access signal for the second memory request signal is generated. And a second access unit.