KR940020842A - Caption subtitle distribution circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the processing of a caption signal. A TV circuit, which is generally used, inputs the output of a caption decoder into the color matrix part of a double scan TV, and the caption is doubled in length in comparison with the normal TV. There is a problem that is large, the length of half is hidden.

Accordingly, the present invention uses the caption decoder subtitle output reference clock as the write clock for the memory and the signal used for the double speed of the main screen as the read clock in order to solve the defects of the conventional TV circuit as described above. The present invention provides a caption caption double speed circuit for generating a clock signal of a scan TV.

Description

Caption subtitle distribution circuit

Since this is an open matter, no full text was included.

1 is a conventional TV circuit diagram in which a caption decoder is applied to a normal scan TV,

2 is a caption caption double speed circuit diagram of the present invention;

3 is a waveform diagram of each part of FIG.

4 is a diagram for explaining the effect of asynchronous clock.

Claims (9)

A video signal that receives the composite video signal Vin and separates the luminance and color signals, stores the data in the line memory unit 15, and outputs the data at double speed to implement the video signal doubled through the color matrix unit 18. A caption signal generation unit 10 detects a caption signal from the complex video signal Vin and decodes the caption signal, and then synthesizes a corresponding character with on-screen display data to generate a caption signal with a double-speed horizontal frequency signal. 20, a blanking signal generator 90 for generating vertical and horizontal blanking signals for displaying caption signals in the caption signal generator 20, and timing generation for generating timing signals necessary for the overall operation of the system; A caption caption double speed circuit comprising: a section (100). The caption signal generating unit 20 of claim 1, wherein the caption signal generating unit 20 generates a caption horizontal position designation unit 40 for generating a control signal for designating a horizontal position of the caption subtitles, and a caption signal carried on the last line of the vertical blanking signal. Caption decoder 30 for generating a corresponding character by decoding and receiving information on the horizontal position of the caption from the caption horizontal position designation unit 40 and outputting a caption signal corresponding thereto, and the caption decoder 30. Clock signal (WCK) and reset write signal for storing caption data from A clock generation unit 70 for generating a subfield), a line memory 80 for inputting caption caption data from the caption decoder 30 and delaying it by 1H, a microcomputer 60 for outputting on-screen display data, and And a caption caption sub-speed circuit comprising a data synthesizing unit (50) for synthesizing the caption caption signal output from the line memory (80) and the microcomputer (60) and the on-screen display signal. The flip-flop of claim 2, wherein the caption horizontal position designation unit 40 has an output terminal of the buffers I1 and I2 to which the doubled horizontal blanking signal is applied and is connected to a clock terminal CK of the flip-flop FF1. The inverted output terminal Q of FF1 is commonly connected to the input terminal D and one input terminal of the NAND gate ND1, and the output side of the buffer I2 is connected to the other input terminal of the NAND gate ND1, and the flip The reset write signal (to the clear terminal CLR of the flop FF1) Caption caption speeding circuit, characterized in that is applied. 4. The caption subtitle assignment circuit according to claim 2 or 3, wherein the subtitle horizontal position designating unit (40) outputs an active signal during the horizontal retrace period. 3. The caption decoder (30) of claim 2, wherein the caption decoder (30) stops the reference clock (LC OSC OUT) for caption output when the output of the caption horizontal positioning unit (40) is activated and outputs a caption position designation signal. Caption caption speeding circuit characterized in that. 3. The clock generator of claim 2, wherein the clock generator 70 is a reset write signal. ) Is output to the line memory 80 through the time delay and the gate (I3, I4, OR5, AD1) acting as a buffer and the 4fsc clock is passed through the buffer (I5, I6) and then the reset write signal ( ) Is inputted to OR gate OR6 and the output of OR gate OR6 is coupled at AND gate AD2 together with reference clock signal LC OSC OUT passing through resistor R1 and buffers I7 and I8. And a caption caption double speed circuit which is logically combined to be output as a write clock signal (WCK) for the line memory (80). 3. The read clock RCK and the reset read signal of the line memory 80 are applied to the line memory 80. ) Is the write clock (WCK) and reset write signal ( Caption caption double speed circuit having a frequency of twice. The horizontal blanking signal (H.BLK) of the line memory 80 is a read enable terminal of the line memory 80 so that the stored caption subtitle data is not output in the horizontal retrace period. Caption caption speed distribution circuit, characterized in that applied to). The data synthesizing unit 50 of claim 2 further includes caption caption data R, G, B, BL of the line memory 80 and on-screen display data R, G, B, of the microcomputer 60. And a plurality of OR gates OR1 to OR4 outputting the data of the same component with respect to BL) to the color matrix unit 18 and outputting the same to each other. ※ Note: The disclosure is based on the initial application.