JPS60132480A - Receiver of still picture signal - Google Patents

Abstract

PURPOSE:To fetch and read the still picture signal to and out of a memory in synchronizing accurately with said signal by detecting the coincidence between an address allocated previously and an address sent from a CPU via a bus. CONSTITUTION:A CPU18 delivers a certain address where an address coder 35 is fixed to an address line 26. A circuit 15 decodes said address and outputs a decoding pulse to an AND circuit 31 and an OR circuit 33 respectively. The pulse supplied to the circuit 33 is supplied as it is as a clock pulse of a 254-bit shift register 34 of a buffer memory 21 to read out a bit of the memory contents. the read-out memory contents are outputted to the circuit 31. In this case, the above-mentioned decoding pulse is applied to the other input of the circuit 31. Therefore the memory contents are outputted as they are to a data line 25 of the CPU18. The above-mentioned actions are repeated and the CPU18 can read successively the bits of the identification signal contained in a still picture signal.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention receives still image signals superimposed and sent during the vertical retrace period of a television signal, and displays characters, figures, etc. on a picture tube. This relates to a still image signal receiving device that displays still images.0 [Background of the Invention] Still image information such as characters and graphics is transmitted using television radio waves without interfering with normal television signals. Several still image broadcasting methods are known. This still image broadcasting method multiplexes and inserts crushed earth image information of a song program into one horizontal scanning period (hereinafter abbreviated as 1H) within the vertical blanking period (hereinafter abbreviated as VBL period) of a television signal, and then receives the signal. The system selects the necessary still image information from among these programs, stores it in a field memory circuit, reads it out, and displays it on the television picture tube. A typical example of this still image broadcasting system is NH
There is a static broadcast C formula (text broadcast system) announced by K Sogo Giken.

(Television Society Television System 9 Circuit Research Fund 11-
4. 1972-s-22, “Television multiplexing system for text information”
reference). The signal format of the still image broadcasting method C and an outline of the receiver will be described below.

FIG. 1 shows a signal waveform in the still image broadcasting O method.

Figure (a) shows the signal waveform when a still image broadcast signal is multiplexed in the 20th horizontal scanning period (hereinafter abbreviated as 20H) of the standard television signal (7) VBL period. , ) shows a detailed waveform diagram of the still image broadcast signal in the 20th H. The still image broadcast signal is as shown in Fig. 1(a).
It is multiplexed in the VBL period of a standard television signal, and its position is 20H in the first field and 283H in the next field. This still image broadcast signal is VBL
, so it does not appear on the screen of an ordinary television receiver because it is within the period.

Further, as shown in FIG. 1(b), the still picture broadcast signal consists of a 14-bit identification signal and a 240-bit still picture information signal, and the transmission speed is the color subcarrier frequency of the television (hereinafter abbreviated as fs).3. 58MHz, 2 and 1 respectively
The frequency is 5.815 times higher. Therefore, each bit is 0.70 μs and 0.17 μs, respectively, and 1H
Medium, identification signal is approximately 9.8μS1 still image information signal is approximately 41μS
9μs, and the entire still image broadcast signal is approximately 51.7μs.
occupies the time. The still picture information signal is formed using a standard television signal 9] (2) a normal binary pulse code with the white level set to logic "1" and the pedestal level set to logic "0".

The identification signals are always a 1-bit signal start identification signal (hereinafter abbreviated as STX) indicating the start of a still image broadcast signal of different logic levels, a 1-bit still image deletion identification signal, and a program signal indicating the type of still image broadcast signal. It consists of a 4-bit identification signal and an 8-bit scanning line number identification signal that specifies the display position on the picture tube.

Furthermore, the still picture information signal is transmitted as is with text and pattern information such as FIlIMe, and if the same program is arranged in 200 lines in the order of arrival, one screen's worth of text and graphics will be reproduced.

FIG. 2 shows the configuration of a conventional receiver that receives the above signal. In FIG. 2, 1 is an antenna, 2 is a cheese, 6 is an intermediate frequency amplification section, 4 is an envelope detection section, 5 is a video signal processing section, 6 is a deflection section, and 7 is a picture tube. The blocks 1D) to 7 above have exactly the same functions as the blocks in a conventional television receiver.

8 is a changeover switch, A is static + hfi! IF reception section input terminal, B is still image reception section output terminal, 10 is static [E double receiver m section. 11 is a still image broadcasting signal extraction circuit, 12 is a field memo circuit, 16 is a mixing circuit, 14 is a control circuit,
15 is a synchronous regeneration circuit, 16 is a timing signal generation circuit,
17 is an operation panel, and 21 is a buffer memory circuit.

The television broadcast that arrived at Antenna 1 'Kameha wa Chi-'
After being periodontalized at step 2 and converted to an intermediate frequency signal, the intermediate!
It is amplified by the R wave amplification/pm section 3. The amplified intermediate frequency signal is detected by the edge detection section 4, becomes a video signal, and is supplied to the changeover switch 8 and the input end fA of the still image reception section 1O. The video signal input from the input terminal A is sent to a synchronous reproduction circuit 15, a still image broadcasting signal sampling circuit 11, and a mixing circuit 13.
supplied to The synchronization reproduction circuit 15 reproduces a vertical synchronization signal, a horizontal synchronization signal, and a color subcarrier signal from the video signal.
The signal is supplied to the timing signal generation circuit 16. Based on these signals, the timing signal generation circuit 16 generates signals necessary for the still image receiving unit 10, such as pulses that are generated only in the horizontal period when the still image broadcast signal is multiplexed, and clock pulses with a frequency of 215 fB or 815 fs. Generates various timing pulses and supplies them to other circuits. Furthermore, the still image broadcast signal extraction circuit 11 receives the input video signal.

Only the still image broadcast signal shown in No. 111(b) is extracted from the image signal. The extracted still image broadcast signal is supplied to the buffer memory circuit 21 and recorded therein, and at the same time, it is also supplied to the control circuit 14. The control circuit 14 selects only the signal having the job specific signal of the program selected by the operation panel 17t' from among the still image broadcast signals and reads it out from the buffer memory circuit 21. Then, only the still image information signal among them is assigned a scanning line number.

The data is controlled to be recorded in the storage area of the field memory circuit 12 corresponding to the display position specified by the code identification signal. At the same time, the control circuit 14 also performs control such as erasing the displayed still image according to the still image erasure identification signal.

The field memory circuit 12 is composed of a digital memory that stores still image information signals for one screen, and usually uses a random access memory (hereinafter referred to as RAM) or a shift register, and has a capacity of 48,000 (240×200).
There are bits. The still image information signal stored in the field memory circuit 12 is read out in synchronization with the scanning of the television screen, and is superimposed on the synchronizing signal portion of the input video signal in the mixing circuit 13 to display a still image. It becomes a video signal.

A video signal for displaying this still image is outputted to the changeover switch 8 via the output terminal B. When the changeover switch 8 is connected to the a side, a normal video signal is selected, and when the changeover switch 8 is connected to the b side, a video signal for displaying a still image is selected. The selected video signal is supplied to the video signal processing unit 5 and the deflection unit 6, where it is subjected to signal processing and reproduces a normal video screen or a still image screen on the receiving tube 7.

The above is an outline of the conventional receiver.

In such a receiver, the configuration of the control circuit 14 is complicated, resulting in a very large circuit scale.

[Purpose of the invention]

In order to eliminate the above-mentioned drawbacks, it is an object of the present invention to provide a still image that can accurately synchronize with still image signals and capture and read out still image signals into a memory when a general-purpose central processing circuit is used. An object of the present invention is to provide a signal receiving device.

[Summary of the Invention] In order to achieve the above object, the present invention provides means for detecting the arrival of a still image signal, interrupts the central processing circuit with the signal indicating the arrival, and detects the received still image signal. If the signal indicates a target program, an address previously assigned to the buffer memory is supplied to the address node. The buffer-r memory decodes this address and transfers the static image signal to the field memory via the data bus to the platform that matches the address assigned to itself.0 [Embodiment of the Invention] ] Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the present invention, and is a block diagram when the present invention is applied to the still image receiving section 10 described above. In FIG. 3, the same parts as in FIG. 2 are designated by the same reference numerals.

In addition, 18 is a central processing unit (hereinafter abbreviated as 0PU),
19 is a still image signal arrival detection circuit; 20 is a C! from the operation panel 17; Operation panel/r that transfers signals to P U 18
Interface circuit 19.22 is a buffer memory clock circuit, 26 is a field memory clock circuit, and 24 is O
A program memory circuit stores instructions to be executed by the P U 18, 25 is a data line, and 26 is an address line.

By using this configuration, it becomes possible to perform all the functions of the control circuit 24 in the conventional receiver shown in FIG. This makes it easy to connect other devices.

Hereinafter, the operation of the apparatus shown in FIG. 3 will be explained in detail using FIGS. 4 and 5. 4 and 5 are circuit block examples in which the circuit block in FIG. 3 is constructed with more detailed circuits, and the same parts are indicated by the same reference numerals. In FIG. 4, 27 is a 7-refloat (hereinafter abbreviated as FF) circuit, 28 is a not (hereinafter abbreviated as NOT) circuit, and 29
is an A-D circuit that converts an analog signal into a binary digital circuit.
Conversion circuits, 60 to 32 are AND (hereinafter abbreviated as AND) circuits, 33 is an OR (hereinafter abbreviated as OR) circuit, 34 is 254
Bit shift register 35 indicates an address decoder circuit. Also, in Fig. 5, 56, ! +7 is NO
T circuit, 38 to 44 are AND circuits, 45 is a 48000-bit random access memory (hereinafter abbreviated as RAM),
46 is an OR circuit, 47 is a latch circuit, and 48 is a 'γ address decoder circuit.

In FIG. 3, the video signal input from the input terminal A of the still image receiving section is input to the still image broadcasting signal extracting circuit 11, as in the case of FIG. The signal is output to the synchronous reproducing circuit 15° mixing circuit 13. In the still image broadcast signal extraction circuit 11, the input video signal is converted into a binary digital signal by the A-D conversion circuit 29 and outputted to the AND circuit 50, where the second DH and The binary digital signal is gated by the 283H pulse, and only the still image broadcast signal is extracted. The extracted still image signal is output to the still image signal arrival detection circuit 19 and the buffer memory circuit 21. On the other hand, in the buffer memory clock circuit 22, the gate of the AND circuit 32 is opened only for the second DH and the 286th H, and the gate of the AND circuit 32 is opened for the second DH and the 286th H,
The 254-bit clock pulse per H is ORed in the OR circuit 33.
The signal is then output to the 254-bit shift register 4 in the buffer memory circuit 21. Therefore, the arriving still image signal is stored as is in the 254-bit shift register 64 in the buffer memory circuit 21 with the bit configuration shown in FIG. 1(b).

In addition, in intervals (times) other than the 20H and 283H, the still image signal stored in the buffer memory circuit 21 is output to the data line 25 of the OPU 18 in the following order. That is, the timing signal generation circuit 1
The 20th H and 285th H pulses from 6 are inverted by degrees Celsius by the NOT circuit 28 of the detection circuit 19 and outputted to the reset input of the FF circuit 27, releasing the reset of the yy circuit 27 for only that period. Since the arriving still image signal is input to the set input of the FF circuit 27, the FF circuit 27 is normally set for 1H, and the 20th or second
It is reset at the end of 83H. The positive logic output signal of the FF circuit 27 is the output signal of the detection circuit 19 as it is, and is outputted to the 0PU 18 as an interrupt signal. At this time, it is possible to simply output the pulses that are output only at the 20H and 283H to 0P018, but by adopting the above configuration, it is possible to accurately know the arrival of the still image signal.

The OPU 18 starts determining the identification signal of the still image signal when the positive logic output signal of the FF circuit 27 falls. That is, the 0PU 18 outputs a certain address to which the address decoder circuit 65 is determined on the address line 26. The circuit 65 decodes this address and outputs a decode pulse to the AND circuit 31 and the OR circuit 33. The pulse input to 0R35 is directly applied as a clock pulse to the 254-bit shift register 34 of the buffer memory circuit 21, and one bit of the stored contents is read out. The read memory content is output to the AND circuit 31, but at this time, since the decode pulse is applied to the other input of the AND circuit 61, the memory content is output as is to the data line 25 of QPU 1B. is output to. By repeating the above operations, the 0PU 18 can successively read each bit of the identification signal in the still image signal. The read identification signal is compared with a program selection signal input from the operation panel 17 to the data line 25 via the operation panel interface circuit 20, and it is determined whether the program is selected by the operation panel 17 or not. If the arriving still image signal is not the selected program, the 0PU 18 waits until the arrival of the next still image signal is detected. However, if the arriving still image signal is the selected program, 11? stopff
It is determined whether the J-extinguisher identification signal is logic "1" or not, and if it is logic "1", all the memory contents of the field memory circuit 12 are erased.Then, the storage area of the memory circuit 12 is scanned. The arrived still image information 240 pits are transferred to the portion corresponding to the scanning line position designated by the 8-bit line number identification signal.

On the other hand, an example of the configuration of the field memory circuit 12 is shown in FIG. It is configured to be separated from the That is, the display pulse outputted from the timing signal generation circuit 16 and which becomes logic "0" only during display closes the gates of the AND circuits 42 and 44 in the logic "o" section, is logically inverted by the NOT circuit 37, and is outputted from the AND circuit. Therefore, the address pulse outputted from the timing signal generation circuit 16 is outputted to the 480 '00 pin-RAM via the AND circuit 43 and the OR circuit 46.Similarly, the NOT circuit 56 AND circuit 38.40 connected via
Since each data of 41 is the output signal of the AND circuit 44 or the logic "θ", it is closed.

Therefore, the output logic "o" of the AND circuit 41 sets the RAM to the read state.
The stored contents are read out one after another in response to changes in the address pulse output from the timing signal generation circuit 16.1. The read memory contents are output from the field memory circuit 12 via an AND circuit 39.

Next, when the display pulse is logic "1", the gates of the AND circuits 39 and 43 are closed and the gates of the AND circuits 42 and 44 are opened. The circuit 48 is
Latch circuits 47 are connected to the data lines 25, and the output of the address decoder circuit 48 is connected to the AND circuit 44.
and the output of the latch circuit 47 are connected to the AND circuit 42. For this reason, 0PU1
When the address decoder circuit 48 outputs a predetermined address to the address line 26, the data simultaneously output to the data line 25 is latched as is by the latch circuit 47, and the AND circuit 42. It is outputted to the RAM via the OR circuit 46 (48,000 bits).

At the same time, the output signal of the AND circuit 44 becomes logic "1", so the gates of the AND circuits 38, 40 and 41 are opened.
0 pin) RAM2S can now be controlled, the address decoder circuit 48 specifies the predetermined address on the address line 26, the address of the bit whose contents in the RAM 45 is to be changed on the data line 25, and at the same time the AN
It is possible to indicate on the data line 25 connected to the D circuit 41 whether the contents of the specified bit are to be read or immersed therein. Also, the information to be written to the specified bit is written to the data line 25 connected to the A and N D circuits 41.
The read information can be shown in the AND circuit di8.
is shown on data line 25 connected to. Therefore, during this period, the transfer of the 240-bit still image information signal is r+
■It is Noh.

Note that in the above explanation, it was assumed that the address setting of the 48,000-bit RAM and the specification of the read/write were performed at the same time. A CPU is required that can process 2 bits of write/read information, totaling 19 bits or more, in parallel. However, if the number of latches in the latch circuit 47 is set to two or three times, the widely used 16-bit or 8-bit parallel processing OPU can also be sufficiently used.

As described above, when the arriving still image signal is the selected program, the display signal output from the timing signal generation circuit 16 is between logic "1n".
The 0PU 18 controls the 240-bit still image information signal stored in the buffer memory circuit 21 to be transferred to the field memory circuit 12. At this time, since the display nozzle output from the timing signal generation circuit 16 is also supplied to the 0PU 18, it can be determined whether or not the still image information signal can be transferred to the field memory circuit 12. All such operations performed by the OPU 18 are stored as instructions in the program memory circuit 24.

Further, as in the case of FIG. 2, the synchronization reproduction circuit 15 reproduces various TV synchronization signals and supplies them to the timing signal generation circuit 16.
Various timing signals required by the circuits shown in FIGS. 4, 5, and 5 are generated.

Next, while the display pulse is at logic "0", a still image information signal is read out from the field memory circuit 12,
As in the case of FIG. 2, the mixing circuit 13 converts the signal into a video signal for displaying a still image, and outputs it to the output terminal B of the still image receiving section.

The above is the details of the operation of the device shown in FIG.
FIG. 5 is just an example of the configuration, and the configuration is not limited to this. For example, the buffer memory circuit 21 has the same configuration as that used in the field memory circuit 12,
RAM that can store 254 bits or more may be used. In addition, the program memory circuit P624 is also used as the field memory circuit 12, so that the 0PU18 and the field memory are not separated, and the still image information signal is recorded as data in the program memory circuit 24 and read out by direct memory access. Even if parallel data is converted into serial data and supplied to the mixing circuit 13, it is possible to provide the same function. [Effects of the Invention] According to the present invention, a general-purpose central processing circuit is used. In this case, the still image signal can be written to and read from the memory in accurate cycles with the still image signal.

[Brief explanation of the drawing]

11i4(a) and (b) are signal waveform diagrams of television signals in the NHK still image broadcast system, which is an example of the still image broadcast system, and FIG. 2 shows the number of still images in the conventional system. A block diagram of a transceiver; FIG. 5 is a block diagram of a still image signal receiving section to which the present invention is applied in a still image broadcast receiver;
5 and 5 are circuit block diagrams showing an example of a case where the circuit block in FIG. 5 is constructed with a more detailed circuit. 1... Antenna 2... Tuner... Intermediate frequency amplification section 4... Envelope detection section 5... Scissors image signal processing section 6... Deflection section 7... Image receiving section. 1O...Stationary shield part 11...Still image broadcasting signal extraction circuit 12...Field memory circuit 14/Control circuit 16...Timing (g-number generation circuit 18-Central processing unit 21... Buffts memory circuit 25... Data line 26 Address line 64... 254 bit shift register 55 Address decoder circuit 46... 48000 bit RAM 47... Latch circuit 48... Address decoder circuit Figure 2 1 Figure 3 4 Figure 1R Figure 5

Claims (1)

[Claims] 1) In a still image signal receiving device that receives a still image signal multiplexed with a television signal and transmitted, a still image signal receiving device that extracts the still image signal from the television signal in synchronization with a synchronization signal included in the television signal. an image signal extracting means, a program storage circuit that stores processing procedures in advance, and an auxiliary memory connected to the still image signal extracting means and temporarily storing the still image signal extracted by the still image signal extracting means. means, a main memory means for storing information displayed on a display screen, and a still image signal connected to the program storage circuit and stored in the auxiliary storage means according to a predetermined processing procedure stored in the program storage circuit. a central processing circuit that reads and writes information to the main memory circuit as information to be displayed on a display screen; and a central processing circuit that is connected to the still image signal extracting means and generates an interrupt signal to the central processing circuit in response to an output of the still image signal extracting means. occurs,
Still image detection means for supplying to the central processing circuit; a bus connecting the central processing circuit to the auxiliary storage means and the main storage means; timing signal generating means for generating a timing signal for controlling writing of still image signals into the auxiliary storage means; an address decoder that detects a match with an address sent via the bus, and supplies a read signal to the auxiliary storage means when a match is detected; A still image signal receiving device characterized by reading a still image signal.