JPS5916272B2 - Digital signal storage display circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention is a random access memory (hereinafter referred to as RAM).
The present invention relates to a digital signal storage and display circuit using.

Conventionally, digital signal storage and display circuits that store video signals input at low speed from a signal source such as a tape recorder and display the stored contents on a television receiver at high speed have adopted shift registers as storage elements. It is necessary to circulate the stored contents each time storage or reading is performed, and in order to gain circulation time, it is necessary to add a buffer memory for temporarily storing the video signal before the shift register.

As a result, storage and readout operations have become complicated, resulting in malfunctions and increased costs. SUMMARY OF THE INVENTION Therefore, the present invention proposes a digital signal storage/display circuit employing a RAM that can immediately perform reading and writing at any location by specifying a code based on the above-mentioned drawbacks.

The present invention will be described in detail below according to an illustrative embodiment.

In this embodiment, when displaying 4 stages of stored information on 18 display stages consisting of 16 horizontal scanning lines per field, the width of the display row is adjusted according to the size of the character to be displayed. It is intended to be changed in units of stages (see Figure 1). The arrangement of the input signals is as shown in Figure 2A, with a control signal C for predicting the arrival of the video signal, a display format command signal specifying the display format, and a control signal C for predicting the arrival of the video signal VI and audio signal. Predicted no-signal section NE,
It is composed of a series of signals arranged in the order of audio signal AU.
Note that the control signal C is an audio signal AU video signal V.
It is a signal consisting of a special combination of frequencies that can be distinguished from the display format command signal. It consists of a display signal (second
Figure C), the video signal V is previously connected to the sub-pilot signal SP.
The digital signal group B is a set of digital signal group B consisting of 16 digital signals arranged as a - group and a main pilot signal MP arranged in front of it, and the audio signal AU is a signal in the normal audio band. The contents of the display signal U and the digital video signal D are 117 or 108 digital signals, 811 of the display signal U represents a display area, 701 represents a non-display area, and Nll of the digital video signal D represents white. The character part "0" represents a black background, and considering that the input signal is played from an audio tape recorder, '11l is divided into three wavelengths of 6 MV sine waves (0
．． 5 msec), 10n for 2 wavelengths of sine wave of 4K section (0
．． The sub-pilot signal is a 2KHZ sine wave with one wavelength (0.5msec), and the main pilot signal is a 2KHZ sine wave with two wavelengths (1msec).
c), FS modulation is performed for each (Fig. 2E).
As shown in Figure 3, the above signal is transmitted to the tape recorder TP.
When the control signal C is inputted, the control detection circuit CN detects the control signal C, and its output sets the first flip-flop FF1, triggers the first monostable multi-MO1, and clears the storage contents of all memory elements. The set first flip-flop output switches the signal switching circuit CH to the video signal side, and the FS-modulated display format command signal K and video signal I are input to the FS demodulation circuit DM and converted into digital signals (Fig. 4a). converted. The converted digital signal is input to first and second waveform shaping circuits CPl and CP2 which waveform shape the positive and negative parts, respectively, and output the display signal and digital video signal (FIG. 4b) and the main waveform shaping circuit. - Separated and shaped into sub-pilot signals (Fig. 4c). The first waveform shaping circuit CP
The output of 1 is converted into a digital video signal D by a switching gate GT operating at the output of the first monostable multi-MOl, whose metastable period is selected to be larger than the display format command signal input period.
is input to the memory circuit side, and the display signal U is input to the code designation circuit side. Further, the output of the second waveform shaping circuit CP2 which derives both the main and sub pilot signals is converted into a sampling pulse S by delaying the rising edge of the output of the second waveform shaping circuit in a delayed pulse generation circuit DL, and is converted into a sampling pulse S which is a delayed rising part of the output of the second waveform shaping circuit CP2. The signal is input to the circuit CD and the first and second triggerable monomultis RM1 and RM2. The first triggerable monomulti is continuously triggered and maintains a quasi-stable state as long as the sampling pulse S is input at intervals of about 1.5 msec or less, so the code designation circuit CD is connected to the main circuit only during the period corresponding to the main pilot signal. Input pilot pulse. The second retriggerable monomulti circuit RM2 sets the quasi-stable period to about 5 msec, detects the end of the sampling pulse S, resets the first flip-flop FFl, and switches the signal switching circuit CH.
Switch to the audio circuit side. The code designation circuit CD inputs the display format command signal K by the switching gate output, the first monostable monomulti output, and the sampling pulse, and the code designation circuit CD inputs the display format command signal K based on the switching gate output, the first monostable monomultiple output, and the sampling pulse. The write code signal WC for the main memory circuit MM is generated by multiple outputs, and the write code signal WC for the main memory circuit MM is generated by the horizontal synchronization signal H and vertical synchronization signal V input from the television receiver TV and the oscillator output in the code signal designation circuit. It generates a read code signal RC for the input signal, and also generates a write pulse signal WR and a display period detection signal DP.

The code selection circuit CS, which receives the write code signal WC and the read code signal RC, separately receives a horizontal synchronization signal H.
The write pulse signal WR input in conjunction with
Either a write code or a read code is selected and input to the main memory circuit MM together with the write pulse signal WR.

Therefore, the main memory circuit MM receives the write code signal W.
When C is input, the digital video signal D is written to a predetermined position one by one, and when the read code signal RC is input, the stored digital video signals D are sequentially read out and passed through the display gate DG to the video signal conversion circuit VM. After converting the signal into a video signal, the signal is further converted to a high frequency by a high frequency conversion circuit RF, and is input to the antenna terminal of the television receiver TV. Therefore, the television receiver displays a series of sentences while completing each character horizontally within a predetermined width within a cathode ray tube, and after the display is completed, outputs an audio signal from a speaker.

The code designation circuit CD, code selection circuit CS, main memory circuit MM, and main circuits within the code designation circuit will be explained below.

First, as shown in FIG. 3, the code designation circuit CD is activated by the sampling pulse S inputted through the first AND gate A1, which is open when the first monostable multi-output e is in the high state, to the first shift register. Eight display signals U are input to SRl and the second shift register SR2.

The first shift register SRl for deriving the write code signal WC has the first bit Q1 set to NO8 and a display signal for the following 8 bits being input, and the second bit Q2 set to Nll, that is, the display starts. The second pulse is kept open by the shift pulse control circuit ST until the stage is detected.
the first shift register SRl via the AND gate A2;
A shift pulse is input to , and the second bit Q2 becomes 11.
1 is detected by the shift pulse control circuit ST, the second AND gate A2 is closed, and the shift is completed.

The second bit Q2 is set to 11 degrees, and the second and subsequent 4-bit outputs of the first shift register ST, which is in a stationary state, are input to the line width detection circuit LW, and the continuous state of the second and subsequent outputs 111, that is, the display line. Detects the width of the input main pilot pulse m and divides the input main pilot pulse m according to the output. It is input to the horizontal axis write counting circuit WX and counted.

Also, a scanning write counting circuit W that specifies the horizontal scanning line in the display stage.
H uses the sampling pulse S as input to cyclically change the designated writing position. Furthermore, the area write counting circuit WE that specifies the write area in the main memory circuit MM is
In order to count the recorded areas, specify the output of the written area counting circuit PE that counts the number of 01'' passing through the first bit of the shift register, and specify the designated area among the areas being written. The outputs of the frequency division counting circuits in the variable frequency dividing circuit DV are added.Therefore, the horizontal axis write counting circuit W
X, a write code signal is created by the scanning write counting circuit WH and the area writing counting circuit WE. That is, the scanning write counting circuit WH counts the sampling pulses S.
In order to specify the writing position with respect to the horizontal scanning line during display, the specified position of the digital signal D for 16 pieces of one block is changed cyclically, and the count value of the written area is changed,
The area write counting circuit WE, which adds the count value of the area corresponding to a predetermined writing stage in the width direction of the line being written, specifies the writing area corresponding to the display stage on the display screen. The horizontal axis write counting circuit WX, which counts the frequency-divided output of the main pilot pulse, changes in a stepwise and cyclical manner according to the displayed width of the displayed line and the written column. In order to sequentially designate a display line along the width direction, the count value is sequentially increased each time a display line is written in the width direction. On the other hand, the circuit that includes the second shift register SR2 and generates the read code signal is the fifth shift register.
As shown in the lower part of the figure, two counting circuits for specifying the readout code are connected to the horizontal synchronizing signal H of the television receiver and the output of the display pulse oscillator, one horizontal scanning line along the horizontal scanning line. A horizontal axis readout specifying circuit RX sequentially and cyclically specifies the code of the minute, and horizontal and vertical synchronization signals V and H of the television receiver and a display format command signal K in the second shift register. The horizontal axis write counting circuit W includes a vertical axis read counting circuit RY that specifies a part of the read code signal RC with respect to a scanning position in the vertical axis direction of the scanning line.
X and each output of the horizontal axis read counting circuit RX are made to correspond to each other, and the scanning write counting circuit WH and the area writing counting circuit W
E and each output of the vertical axis read counting circuit RY are made to correspond.

Therefore, 5MHf! ．． The pulse of the display oscillator 0S that oscillates from the Xth to 25th pulse starting from the horizontal synchronizing signal H.
Six pulses are sent to the fourth gate by the first gate control circuit BXl.
Since the signal is supplied to the horizontal axis readout counting circuit RX via the AND gate A4, the counting circuit RX has a count value of 2 for each horizontal scanning line.
56 and designates a part of the read code RC. Further, the second gate control circuit BX2 uses the vertical synchronization signal V as a starting point to derive 128 horizontal synchronization signals H from the Y-th signal from the fifth AND gate A5, and sends the output of the fifth AND gate A5 to the frequency dividing circuit. The frequency is divided by 1/16 at DN, and the display signal selection circuit CC, which sequentially switches and selects the output of the second shift register SR2, is operated by the scanning stage counting circuit LC, which counts the frequency-divided output. The selection circuit outputs the horizontal synchronizing signal H by opening the sixth AND gate A6 only when the television receiver TV scans the stage to be displayed.
Let it pass. The passed horizontal synchronizing signal H is input to the vertical axis read counting circuit RY, and specifies a part of the read code RC. Furthermore, the sampling pulse S and the horizontal synchronization signal H
The write/read designation circuit WP, which receives the input signal, immediately generates a write pulse outside the display period during scanning in relation to the horizontal synchronizing signal H after detecting the sampling pulse S, and detects the end of the write operation. The inverted output of the third bit of the area write counting circuit WE is connected to the seventh AND gate A which inputs the write pulse.
7 is kept open only during writing, and the write pulse signal W
Derive R. Furthermore, an eighth AND gate A8 inputting the output of the display signal selection circuit CC and the output of the first gate control circuit BXl outputs the control output of the display gate DG which is in the 1 state only during the display period. Derive DP. The specific circuits of the line width detection circuit LW, variable frequency divider circuit D, shift pulse control circuit ST, and write/read designation circuit PD in the code designation circuit CD configured as described above are shown in FIG. This is as shown in FIGS. 7 and 8, respectively.

As shown in FIG.
The first output K1 is an inverted output of the output derived from the ninth AND gate A9 which receives the outputs of the fourth bits Q2 and Q3, the output of the fourth bit Q4 of the first shift register SRl and the output of the fourth bit Q4 of the first shift register SRl. a second output K2 which is an inverted output of the output derived from the tenth AND gate AlO which receives the nine AND gate output; and the first shift register SR.
A third output K3 is an inverted output of the output derived from the 11th AND gate All whose inputs are the output of the fifth bit Q5 of l and the 10th AND gate output, and the output derived from the 11th AND gate All. The output of the display width detection circuit consisting of each output of the fourth output K4 is, when the display width is one stage, only the first output K1 is in state 1), and when the display width is two stages, the first output K1 is in state 1). State 11 The second output K2 is set to "...A state", and the first and second outputs Kl and K2 are set to 1 when there are three stages.
When the low state 1 third output K3 is set to I"...I state "I", the first, second, and third outputs Kl, K2, and K3 are set to 1 when there are four stages.
The fourth output K4 in the low state 7 is brought into the high state.

Further, the frequency division counting circuit BC which inputs and counts the main pilot pulse m is configured to be cleared by the frequency division output, and the main pilot pulse m and the first output K
1, the output of the 13th AND gate Al3, which receives the second bit Q2 of the dividing circuit BC and the second output K2, and the frequency dividing circuit. A fourteenth circuit whose inputs are the first and second bits Ql, Q2 of the counting circuit BC and the third output K3.
A first gate whose inputs are the output of the AND gate Al4, the third bit Q3 of the frequency dividing counting circuit BC, and the fourth output.
A third OR gate 03 which receives each output of the 5-AND gate Al, outputs the sum as the output of the variable frequency divider circuit.

Therefore, when the display width is one stage, the undivided main pilot pulse is derived from the first output K1 via the twelfth AND gate Al2, which is in the open state, and when the display width is two stages, the main pilot pulse is derived from the second output, which is in the open state. A 1/2 frequency division output that detects that the frequency division counting circuit BC has counted 8211 is derived from the 13th AND gate Al3, and when there are three stages, the 14th AND gate in an open state is output by the third output K3. Al4
A 1/3 frequency division output that detects that the frequency division counting circuit BC has counted 131 is derived, and when there are four stages, the 15th AND gate Al5 in the open state is generated by the fourth output K4.
A 1/4 frequency division output is respectively derived to detect that the frequency division count has counted "4", and the frequency division counting circuit DV performs a counting operation cyclically within the range of the frequency division value. As shown in FIG. 7, the shift pulse control circuit ST is connected to the first monostable via a sixteenth AND gate Al6 which is open when the second bit Q2 of the first shift register SRl is "01". When the second and third flip-flops FF2 and FF3 are reset by the falling output of the multi-output e, the third
The inverted output of the flip-flop FF3 opens the second AND gate A2, inputs the horizontal synchronizing signal H as the shift pulse to the first shift register SRl, and 111n is shifted to the second bit Q2 of the shift register SRl. Then, the rising pulse passes through the output inverting circuit N to the second flip-flop FF2, and the falling pulse passes through the open 17th AND gate Al7 and the output inverting circuit N to the third flip-flop FF3. FF2 and FF3 are set so that the inverted output of the third flip-flop FF3 becomes the second flip-flop.
The AND gate A2 is closed and the shift is temporarily stopped.

Thereafter, due to the inverted output of the 9th bit Q9 of the horizontal axis write counting circuit WX, which detects that the writing of one line of characters has been completed, the falling pulse again passes through the fourth OR gate 04 and becomes the second 3 flip-flops FF2 and FF3 are reset to open the second AND gate A2, and the second bit Q of the first shift register SRl is reset.
The first shift register SRl continues to be shifted until the second line changes from 101 to ``11'', that is, a rising pulse is generated, and the next write row is detected and the shifting is stopped. As shown in FIG. 8, the 18th AND gate Al8, which is opened by the output of the fourth flip-flop FF4 set by the sampling pulse, immediately passes the horizontal synchronizing signal H and triggers the second monostable multi MO2. A write signal is generated for a certain period of time before the display operation, and the fourth flip-flop FF4 is reset at the fall of the signal.

A code selection circuit CS to which the write code signal WC and read code signal RC derived from the code designation circuit CD having the above-mentioned configuration is inputted manually selects the corresponding bits of both code signals as shown in FIG. Signal selection circuit D1-D
One code signal is selected by inputting it to l4.

For example, as shown in FIG. 10, the first input signal selection circuit D1 opens the 20th AND gate A2O when the write pulse signal is in the 11 low state 1, that is, there is no signal.
The first bit output X/ of the output code signal RC is derived, and when the write pulse signal is in the 11 high state 1, that is, the pulse arrives, the 19th AND gate Al9 is opened and the first bit output X1 of the write code signal WC is derived. do. Therefore, the code 5 signal selected by the code selection circuit CS is input to the main memory circuit MM shown in FIG. However, the RAM, which is a storage element, cannot follow changes in the read code signal. Therefore, in this embodiment, a multiplexer and a diplexer are used to convert the digital video signal D6 input in series.
is sequentially distributed and stored in four memories M1 to M4 having the same code signal, and digital video signals D stored in parallel with the same code signal are sequentially selected and taken out in series. There is. Therefore, the lower two bits of the input code signal are sent to a first multiplexer MP2 that distributes the input digital video signal, a second multiplexer MP2 that distributes the write/read signal, and a diplexer that sequentially selects the read digital video signal. The first and second
Multiplexers MPl, MP2 and diplexer DP are operated at high speed, and the memories M1 to M4, whose codes are specified by the upper 12 bits of the code signal, have a reading speed of 1.
It is sufficient to respond at a speed of /4. The write pulse signal WR sets each memory in a read state when there is no signal other than when a write pulse arrives, and generates a read code from the code designation circuit CD at least cyclically every time the television receiver horizontally scans. A portion of the signal constantly refreshes the entire contents of the RAM, so that the stored contents are never erased.

Therefore, according to the present invention, since a RAM is used as a storage element, there is no need for a buffer memory on the write side or a means for shifting the memory, and the incoming video signal that is input can be directly stored, resulting in reliable operation and cost reduction. can be expected.

[Brief explanation of the drawing]

The figures are all diagrams for explaining one embodiment of the present invention, and FIG. 1 is a diagram showing the display area of a television receiver, FIG. 2 is a diagram showing the contents of the playback output of a tape recorder, and FIG. 3
The figure is a schematic block diagram of this embodiment, Figure 4 is a waveform diagram of the main part in the block diagram of Figure 3, Figure 5 is a detailed block diagram of the code designation circuit in the same block diagram, and Figure 6 is FIG. 7 is a more detailed block diagram of the line width detection circuit LW and variable frequency divider circuit DV in the block diagram of the code designation circuit, and FIG. 7 is a more detailed block diagram showing the shift pulse control circuit in the block diagram of the code designation circuit. 8 is a more detailed block diagram showing the write/read designation circuit in the block diagram of the code signal designation circuit, and FIG. 9 is a detailed block diagram of the code selection circuit in the block diagram of FIG. 3. , FIG. 10 shows a more detailed block diagram showing the input signal selection circuit in the code selection circuit, and FIG. 11 shows a detailed block diagram showing the main memory circuit in the block diagram of FIG. 3.

Claims (1)

[Claims] 1. In a digital signal storage and display device that stores a video signal that is input at low speed and asynchronously with respect to a horizontal synchronization signal of a television receiver in a random access memory, and displays the stored contents as a static text on a television receiver at high speed, A write code designation circuit that designates a write code based on a pilot signal in the video signal and/or an input display format command signal, both horizontal and vertical synchronization signals given from the television receiver, and/or the display command. a read code designation circuit that designates a read code based on a signal; a write/read designation circuit that forms a write pulse from the pilot signal and the horizontal synchronization signal; A code selection circuit that derives a write code only, and a main memory circuit that writes and reads a video signal to and from a random access memory using the output of the write/read designation circuit and the output of the code selection circuit. Digital signal storage and display circuit.