JPS6126272B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a synthesis and separation display circuit which is effective when employed in a digital signal storage and display device that displays digital signals that are input sequentially regardless of storage operations as static characters together with already stored contents. Regarding.

When storing a digital signal that is reproduced and demodulated at a slower speed than a tape recorder and displaying multiple lines of characters consisting of horizontally arranged white static characters on a television screen, the digital signal that is reproduced and demodulated is Since signals are input at low speed, there are various restrictions on display methods and the like. That is, since it takes a long time to complete storage, it is necessary to display the information while it is being stored. Furthermore, if digital information is stored along the horizontal scanning line, there is a drawback that the contents cannot be read until the character line for one line is completed. It is also necessary to arrange the input digital signals so that they can be completed one by one and displayed in reading order. Furthermore, the width of the character line to be displayed needs to be widened when displaying complex characters or depending on the content of the characters to be displayed, and the number of digital signals to be stored vertically regarding the character string may be increased as necessary. It also needs to be changed.

Accordingly, the present invention relates to a composition/separation display circuit that determines and stores a storage position in a memory based on a storage format command signal inputted at the start of storage so that the width of a character line to be displayed can be changed for each line.

The present invention will be described in detail below according to an illustrative embodiment. First, in this embodiment, the unit width of a display character line is composed of 16 horizontal scanning lines (FIG. 1A).
In order to display over the main horizontal scanning line (n<8 positive integer), 16 digital signals are treated as one signal group B, and a sub-pilot signal SP is placed in front of each digital signal D. Also, signal group B
A main pilot signal MP is placed at the beginning of each (Fig. 1B). Furthermore, in order to reliably record and reproduce such signals on a tape recorder, the digital signal corresponding to "white" or letters is a 6KHz sine wave with three wavelengths (0.5msec), and the digital signal corresponding to "black" or ground is a 4KHz digital signal. Two wavelengths of sine wave (0.5m
sec), the sub pilot signal SP is a 1KHz sine wave with one wavelength (0.5 msec), and the main pilot signal MP is
It is FS modulated as a 1KHz sine wave with two wavelengths (1msec) (Figure 1C).

As shown in FIG. 2A, the video signal VI, which is a series of digital information groups, is preceded by a control signal C and a command signal K, and is followed by an audio signal AU with a no-signal period in between. Each is arranged. First, the control signal is the video signal VI
The command signal K consists of a combination of special frequencies not included in the audio signal AU, and the command signal K is a signal obtained by FS modulating the eight display signals U via the sub-pilot signal SP, similar to the contents of the digital signal group. It is. Note that the audio signal AU is a signal in a normal audio band.

As shown in FIG _. 3 _, the digital signal storage/display device inputs the above-mentioned signals, and as shown in _FIG . It is displayed using horizontal scanning lines, and in the horizontal direction, from X ₁ /256 to X ₁ +X ₂ /256 when viewed from the starting end of the horizontal scanning line.
It is intended to be displayed over the following range.

The configuration of the digital signal storage and display device will be described in detail below with reference to the block diagram shown in FIG.

A signal input from the tape recorder TP is input to the control signal detection circuit CN and the switching circuit CH. The control detection circuit CN detects the control signal C and generates a pulse.
The flip-flop FF ₁ is set and the first monostable multi MO ₁ is triggered. The output of the first flip-flop _FF1 switches the switching circuit CH to the video circuit side,
The output of MO ₁ (FIG. 2D) switches the selection gate GT to the pulse control circuit PG side at least until the input of the command signal K is completed. Therefore, the command signal K following the control signal C is sent to the FS demodulation circuit DM.
The FS is demodulated, only the display signal is waveform-shaped by the first waveform shaping circuit _CP1 , and is input as a digital signal to the pulse control circuit PG via the selection gate GT. The sub-pilot signal SP in the command signal K is sent to the second waveform shaping circuit after being FS demodulated.
CF ₂ is input to the pulse control circuit PG as a sub-pilot pulse for display signal storage via the delayed pulse generation circuit DL.

Video signal VI input following the command signal K
is demodulated by the FS demodulation circuit DM, as shown in FIG. 5a, and then waveform-shaped separately into a positive part, that is, a digital signal part, and a negative part, that is, a pilot signal part (FIGS. 5b and 5b). c). Therefore, only the digital signal component is taken out from the first waveform shaping circuit _CP1 , and only the pilot signal component for synchronization is taken out from the second waveform shaping circuit _CP2 .
The shaped wave of the pilot signal obtained from the second waveform shaping circuit _CP2 is input to the delayed pulse generation circuit DL, and is converted into a pulse (FIG. 5S) in which the rising edge of the shaped wave is delayed. This pulse is used as a shift pulse for the buffer memory on the input side, so it is input to the pulse control circuit PG and is also input to the first and second retriggerable monomultipliers.
Input to RM ₁ and RM ₂ . The retriggerable monomulti above is a multivibrator that can be triggered even when it is in a metastable state by the input pulse, and the first retriggerable monomulti RM ₁ completes input of the video signal with a metastable period of about 10 msec. The second retriggerable monomulti RM ₂ detects the break in the digital signal group with a metastable period of about 1.5 msec, and resets the first flip-flop FF ₁ . This is for inverting flip-flop _FF2 . Therefore, the first retrigable monomulti RM ₁ that is reset by the output of the first retriggerable monomulti RM 1
The output of the flip-flop FF ₁ switches the switching circuit to the audio circuit side, and the output of the second flip-flop FF ₂ , which is inverted by the output of the second retriggerable monomulti RM ₂ , is connected to the first to fourth AND gates. A ₁ , A ₂ , A ₃ , A ₄ , close the input side of the buffer memory on the side where the input has been completed, open the output side, open the input side of the buffer memory on the side where the transfer has been completed, and close the output side. shall be.

The constituent parts of the pulse control circuit PG will be described in detail below with reference to FIG. The output of the first monostable multi MO ₁ triggered before the input of the command signal K opens the eighth and ninth AND gates A ₈ and A ₉ . Therefore, the display signal U in the command signal K is the seventh AND gate 4.
is closed to prevent the feedback output of the shift register SR, and is input to the shift register SR via the eighth AND gate _A8 , which is open.
The shift pulse S obtained by converting the sub-pilot signal SP in the command signal K and input through the ninth AND gate A ₉ and the first OR gate O ₁ is sequentially stored in the shift register SR. After completion, the eighth and ninth AND gates are closed, and thereafter the display signal U stored in the shift register SR is circulated once per field in conjunction with the horizontal synchronizing signal H issued from the television receiver. Diagram numbers BX, A ₁₆ , and DV ₁ are circuits for this purpose, and the horizontal synchronization signal H is started from the vertical synchronization signal V.
While counting, _{the 17th} AND _gate A ₁₇
The first gate control circuit BX ₁ and 1/
It consists of a first frequency dividing circuit DV ₁ that divides the frequency by 16, and the first frequency dividing circuit DV1 divides the frequency by 16.
The frequency dividing circuit generates shift pulses in synchronization with the scanning position of the television receiver. Display signal U derived from the shift register SR
The television receiver is the (Y ₁ + 1)th ~
It is derived from the tenth AND gate A ₁₀ which is open during the (Y ₁ +Y ₂ )th horizontal scan, that is, during the video display period.

On the other hand, the shift pulse G of the main memory MM which stores the digital signal group transferred from the buffer memory and which supplies the contents to the television receiver is also derived from the pulse control circuit PG. Figure number in Figure 6
OSC, BX ₂ and A ₁₈ are circuits for this purpose, and in order to derive the output of the pulse oscillator OSC, which generates a pulse with a period 256 times that of the horizontal synchronizing signal H, in synchronization with the display operation on the television receiver. The second gate control circuit BX ₂ counts the oscillator OSC output using the horizontal synchronization signal H as a starting point, and is in a quasi-stable state only for the (X ₁ +1)th to (X ₁ +X ₂ )th output. Both outputs of the control circuit BX ₁ cause the output of the pulse oscillator OSC to be controlled by the 18th AND gate A ₁₈ , which becomes open only when the image display area l ₀ to _{l 7} in FIG. 3 is being scanned. is controlled to generate a shift pulse G.

A circuit for generating a write pulse W for transferring the contents of the buffer memory and writing to a predetermined location in the main memory MM will be further explained below. First, the first comparison circuit CF ₁ is a first X binary counter CT ₁ for specifying the position in the X _-axis direction in FIG.
and a second counter that counts the shift pulse G to the main memory MM and displays the scanning position of the television receiver in the X-axis direction,
When the count values of the first and second counters CT ₁ and CT ₂ match, an output is generated. The first counter CT ₁ is
The output of a negation circuit N that inverts the output of the differentiating circuit DF which captures the falling part of the shift register output and generates a pulse, and the write pulse W is divided by 1/16 to write the digital signal group B. It counts the output of the eleventh AND gate A ₁₁ which detects the coincidence of the second monostable monomulti MO ₂ output triggered by the second frequency divider circuit DV ₂ which detects the end. For example, if you want to display three stages, or 48 horizontal scanning lines, the shift register output will go down after the end of writing of the third digital signal group is detected, and 48 digital signals will be stored. Until the end, the designated position in the X-axis direction will not be changed and the 48 digital signals will remain in the Y position.
They are stored in a continuous line in the axial direction. Next, the second comparison circuit CF ₂ outputs the count value of a third counter CT ₃ that counts the shift output to the shift register SR while being cleared by the falling edge of the shift register output, and the write pulse divided by 1/16. 4th counter that counts the output and is cleared by the 11th AND gate output A ₁₁
The purpose is to compare the CT ₄ count values and detect a match. The third counter _CT3 counts the shift pulses input to the shift register SR in order to designate the number of stages to increase when the display width is made to extend over a plurality of stages. The fourth counter CT 4 is a specified side counter that is cleared at the falling edge of , and the fourth counter CT ₄ counts the written digital signal group, and each time it detects the end of storage in the width direction of the display line. This is a counter that is cleared by the output of the eleventh AND gate _A11 that generates an output. Furthermore, the third comparison circuit CF ₃
counts the falling edge of the display signal U derived from the shift register SR, and outputs the output of the fifth counter _CT5 , which is cleared by the vertical synchronization signal V, and the first counter
This is a comparison circuit for display line designation that detects coincidence of the outputs of the sixth counter CT ₆ which counts the output generated when CT ₁ counts X ₂ and generates an output. Said sixth
The counter CT ₆ counts the output generated by the first counter upon detecting the end of the line in order to count the number of lines stored, and specifies _the line to be stored. The number of display lines is counted based on the display output of the shift register SR, which is shifted in conjunction with the display position above.

Therefore, the first, second and third comparison circuits CF ₁ ,
A 12th AND gate that takes the AND of the matching outputs of CF ₂ and CF ₃ and the output of the third flip-flop FF ₃ , which is set upon completion of inputting the digital signal group to the buffer memory and reset upon completion of transfer.
A write pulse can be obtained from _A12 .

The following or further the first buffer memory BM ₁ and the second buffer memory BM 1 .
Shift pulse S ₁ input to buffer memory BM ₂ ,
I will explain about S ₂ . The buffer memory requires a shift pulse S related to the sub-pilot signal SP at the time of input, and a write shift pulse W at the time of transfer, so the shift pulse must be switched.
Such switching is performed by the 13th to 16th AND gates A ₁₃ , A ₁₄ ,
It is done by A ₁₅ and A ₁₆ . For example, when the Q of the second flip-flop FF ₂ output is “1” and “0”,
The second AND gate A ₁ , the third AND gate A ₃ , the 13th AND gate A ₁₃ and the 15th AND gate A ₁₅ in the pulse control circuit are respectively opened, and the second AND gate A ₂ is connected to the second buffer memory BM. ₂ into the input state, the third AND gate A ₃ puts the first buffer memory BM ₁ into the transfer state, and the 13th AND gate
_A13 inputs a write shift pulse W to the first buffer memory _BM1 , and a fifteenth AND gate _A15 inputs a delay pulse S to the second buffer memory _BM2 . Therefore, the delay pulse S associated with the sub-pilot signal SP is input to the second buffer memory _BM2 to which the digital signal group B is input, and the write pulse W is input to the first buffer memory _BM1 on the transfer side.

On the other hand, the first flip-flop output R, which is inverted based on the detection output of the control signal, is connected to the second differentiator circuit.
It is input to DF ₂ and converted into a clear pulse M synchronized with the rising edge of the flip-flop output R, which is then applied to the first and second buffer memories BM ₁ and BM ₂ and the main memory.
Delete the memory contents of MM. Furthermore, the output X of the 19th AND gate that detects the coincidence output of the first and second gate control circuits BX ₁ , BX ₂ and the 10th AND gate A ₁₀ generates an output only during the display period, and the seventh AND gate is opened. state. Furthermore, the shift pulse G input to the main memory MM is logically ANDed by the 20th AND gate A ₂₀ with the output of the 10th AND gate A ₁₀ and the output of the 18th AND gate A ₁₈ in order to generate an output only during display. The output is a shift pulse G.

After detecting the control signal and clearing the buffer memory BM and main memory MM, the pulse control circuit PG having the above-mentioned configuration stores the display signal U, and the digital signal group B inputted following the display signal U is as follows.
The delayed pulse S is input to the buffer memory on the input side. Main memory MM generated in connection with the scanning position of the television receiver TV and the display signal U
The shift pulse G shifts the contents of the main memory MM to the sixth
It is cyclically shifted through the AND gate _A6 and inputted to the television receiver TV through the seventh AND gate _A7 , and at the same time, it is stored in a predetermined value in the main memory MM based on the count values of the display signal U and the write pulse W. In order to store the digital signal D in the position, the fifth AND gate A ₅ is opened and the sixth AND gate A ₆ is closed at the write pulse W, and a shift for transfer occurs simultaneously with the write pulse W. The pulse causes the main memory MM to store the information.

The video signal derived from the seventh AND gate _A7 by the above operation is connected to the video signal conversion circuit VW.
Through the RF conversion circuit RF, the television receiver TV
input to the antenna terminal.

Video signal VI played from tape recorder TP
When the first retriggerable monomulti RM ₁ generates an output upon detecting the end of the first flip-flop
FF ₁ is inverted, the switching circuit CH is switched to the audio circuit, and the audio signal AU following the video signal VI is sent to the audio amplifier.
After amplification to AA, the video signal VI is sent to the high frequency conversion circuit RF.
It is configured to perform RF conversion along with the RF conversion.

Therefore, according to the present invention, the width of the characters to be displayed can be changed for each line, and the size of the characters can also be changed depending on the content of the display.

[Brief explanation of the drawing]

The figures are diagrams showing one embodiment of the present invention,
Fig. 1 is a diagram explaining the contents of the video signal, Fig. 2 is a diagram explaining the content of the display signal, Fig. 3 is a diagram showing the display position on the display screen of the television receiver, and Fig. 4 is a diagram explaining the content of the display signal. , a schematic block diagram of the device of this embodiment,
FIG. 5 is a diagram showing the conversion state of input signals;
6 shows a block diagram showing the pulse control circuit in the block diagram of FIG. 4, respectively. Explanation of main drawing numbers, VI...Video signal, AU...Audio signal, K...Command signal, U...Display signal, SP
...Sub pilot signal, SR...Shift register.

Claims (1)

[Claims] 1. In a digital display device that stores a video signal that is input to a television receiver at low speed and asynchronously, and displays the stored contents at high speed as a static text on the television receiver, a display that is input before the video signal is means for generating a signal for setting a line width in which a video signal is displayed based on a command signal; a means for sequentially and continuously storing a video signal corresponding to the line width in a desired storage position in a storage circuit; A composition/separation display circuit comprising means for deriving the contents of a storage circuit based on the scanning position of a television receiver and the command signal.