JPS6110362Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate control circuit that detects different designated count values in one counting circuit and generates control outputs for the respective gates.

Generally, the number of arriving pulses is counted by a counting circuit, and (M+N) (M, N) of the M pulses are counted by a counting circuit.
is a positive integer) A gate control circuit that generates a control signal for opening the gate only while the gate is open is used in various electronic devices.
Such a gate control circuit was constructed as follows. That is, one of them is to first count the incoming pulses up to M in the first counting circuit, and at the point when M has been counted, set the flip-flop for generating the control signal, and from that point onwards, the incoming pulses are counted up to M. is counted up to N by the second counting circuit, and N
The flip-flop is reset when the number of flip-flops is counted. The other one generates outputs when M and (M+N) incoming pulses are counted by one counting circuit, and the first output sets the above-mentioned flip-flop, and the later output resets it. It was designed to do so. However, such conventional circuits require two counting circuits or (M+N)
Since it requires a counting circuit with a large number of digits (number of bits) that can count up to 1, there is a problem that it cannot be realized at low cost.

Therefore, the present invention uses the maximum value N _o of different designated count values.
The present _invention proposes a gate control circuit that detects a plurality of designated count values using a single counting circuit to open and close a gate.

Below, we will explain in detail an embodiment in which the present invention is applied to a character display device, etc. First, in this embodiment, the unit width of a display character line is composed of 16 horizontal scanning lines (Fig. 1A). 16n pieces (positive integer of n<8)
16 digital signals are treated as one signal group B, and the sub-pilot signal SP is placed before the digital signal D, and the main pilot signal is placed at the beginning of the signal group B. Each MP is arranged (Figure 1B). Furthermore, in order to reliably record and reproduce such signals on a tape recorder, the digital signal corresponding to "white" or characters is 6KHz sine wave three wavelengths (0.5msec), and the digital signal corresponding to "black" or ground is 4KHz. The sub pilot signal SP is a 2KHz sine wave with one wavelength (0.5msec), and the main pilot signal MP is a 2KHz sine wave with two wavelengths (1msec).
It is modulated (Figure 1C). As shown in FIG. 2A, the video signal VI, which is a series of digital information groups, is preceded by a control signal C and a command signal K, and is followed by an audio signal AU with a no-signal period in between. It is arranged. First, the control signal consists of a combination of special frequencies that are not included in the video signal VI and the audio signal AU, and the command signal K is similar to the contents of the digital signal group, and the eight display signals U are sent via the sub-pilot signal SP. This is an FS modulated signal. Note that the audio signal AU is a signal in a normal audio band.

The digital signal storage/display device receives the above-mentioned signals as input, and as shown in FIG _.
+1) Display using the (Y ₁ + Y ₂ )th horizontal scanning line from the first horizontal scanning line, and in the horizontal direction, from X ₁ + 1/256 to X ₁ + X ₂ /25 from the start of the horizontal scanning line.
It is intended to display the range up to 6.

The configuration of the digital signal storage and display device will be described in detail below with reference to the block diagram shown in FIG.

A signal input from the tape recorder TP is input to the control signal detection circuit CN and the switching circuit CH. The control detection circuit CN generates a pulse on the control signal C to set the first flip-flop _FF1 and trigger the first monostable multi _MO1 . The output of the first flip-flop _FF1 switches the switching circuit CH to the video circuit side, and outputs the first monostable multi _MO1.
The output (D in Fig. 2) controls the selection gate GT to the pulse control circuit at least until the input of the command signal K is completed.
Switch to PG side. Therefore, the command signal K following the control signal C is subjected to FS in the FS demodulation circuit DM, and only the display signal is waveform-shaped by the first waveform circuit _CP1 , and then digitally sent to the pulse control circuit PG via the selection gate GT. Input as a signal. Furthermore, the sub pilot signal SP in the command signal K
is FS demodulated and then input as a sub-pilot pulse for display signal storage to the pulse control circuit PG via the second waveform circuit CP ₂ and the delayed pulse generation circuit DL.

Video signal VI input following the command signal K
is demodulated by the FS demodulation circuit DM as shown in FIG. b, c).
Therefore, only the digital signal component is taken out from the first waveform circuit _CP1 , and only the pilot signal component for the same period is taken out from the second waveform circuit _CP2 . The shaped wave of the pilot signal obtained from the second waveform circuit _CP2 is input to the delay pulse generation circuit DL,
The rising edge of the rectified waveform is converted into a delayed pulse (S in FIG. 5). The pulse is input to the pulse control circuit PG to be used as a shift pulse for the buffer memory, and is also used as a shift pulse for the buffer memory.
Input to retriggerable monomulti RM ₁ and RM ₂ .

The above-mentioned retriggerable monomulti is a multivibrator that can be triggered even when in a quasi-stable state by input pulses, and the first retriggerable monomulti RM ₁ inputs a video signal with a quasi-stable period of about 10 msec. Completion is detected, and the first
This is to reset the flip-flop FF ₁ , and the second retriggerable monomulti RM ₂ has a metastable period of about 1.5 msec, detects the break in the digital signal group, and inverts the subsequent second flip-flop FF ₂ . It is for. Therefore, the first flip-flop is reset by the output of the first retriggerable monomulti _RM1 .
The FF ₁ output switches the switching circuit to the audio circuit side and is inverted by the output of the second retriggerable monomulti RM _{2 .}
The outputs of the first to fourth AND gates A ₁ , A ₂ ,
A ₃ and A ₄ are performed to close the input side and open the output side of the buffer memory on the side where the input has been completed, and to open the input side and close the output side of the buffer memory on the side where the transfer has been completed.

The constituent parts of the pulse control circuit PG will be described in detail below with reference to FIG. The output of the first monostable multi MO ₁ triggered before the input of the command signal K opens the eighth and ninth AND gates A ₈ and A ₉ . Therefore, the display signal U in the command signal K is the seventh AND gate G.
is closed to prevent the feedback output of the shift register SR, and is input to the shift register SR via the eighth AND gate _A8 , which is open.
The shift pulse S obtained by converting the sub-pilot signal SP in the command signal K and input through the ninth AND gate A ₉ and the first OR gate O ₁ is sequentially stored in the shift register SR. After completion, the eighth and ninth AND gates are closed, and thereafter the display signal U stored in the shift register SR is circulated once per field in conjunction with the horizontal synchronizing signal H issued from the television receiver. Diagram numbers BX ₁ , A ₁₇ , and DV ₁ are circuits for this purpose, and the horizontal synchronization signal H is
While counting, _{the 17th} AND _gate A ₁₇
The first gate control circuit BX ₁ and 1/
It consists of a first frequency dividing circuit _DV1 which divides the frequency by 16, and this first frequency dividing circuit generates a shift pulse in synchronization with the scanning position of the television receiver. The display signal U derived from the shift register SR is
The television receiver is (Y ₁ + 1)th ~ (Y ₁ +
The 10th AND gate is open during the _Y2 )th horizontal scan, that is, during the video display section.
Derived from A ₁₀ .

On the other hand, the shift pulse G of the main memory MM, which stores the digital signal group transferred from the buffer memory and delivers its contents to the television receiver, is also derived from the pulse control circuit RG. The numbers OSC, BX ₂ , and A ₁₈ in Figure 6 are circuits for this purpose, which synchronize the output of the pulse oscillator OSC, which generates pulses with a frequency 256 times that of the horizontal synchronizing signal H, with the display operation on the television receiver. In order to at least derive the output, the second gate control circuit counts the oscillator OSC output using the horizontal synchronization signal H as a starting point, and is in a quasi-stable state only for the (X ₁ +1)th to (X ₁ + _X2 )th outputs.
By both outputs of BX ₂ and the first control circuit BX ₁ , the third
The 18th AND gate A ₁₈ is open only when the image display area from l ₀ to _{l 7} in the figure is being scanned.
The shift pulse G is generated by controlling the output of the pulse oscillator OSC.

First gate control circuit BX ₁ and second gate control circuit according to the present invention
The gate control circuit BX ₂ will be explained in conjunction with the first gate control circuit BX ₁ in FIG. 7, which has the same configuration as shown in FIGS. 7 and 8, except for the designated count values.
In Fig. 7, CT ₇ is the seventh counter that is cleared by the output of the 21st AND gate A ₂₁ and the vertical synchronization signal V and counts the horizontal synchronization signal H, and CY ₁ is the seventh counter.
The _Y1 detection circuit detects when the count value reaches _Y1 by the AND output of the predetermined bit output of _CT7 , and _CY2 similarly generates an output when the count value reaches _Y2 .
_Y2 detection circuit, _FF5 is set by vertical synchronization signal,
A fifth RS flip-flop, FF ₄ , which is reset by the _Y1 detection circuit output, is a fourth RS flip-flop, which is set by the 21st AND gate output and reset by the _Y2 detection output. Therefore, only when the count value Y ₁ is detected with the vertical synchronization signal as the starting point, the Y ₁ detection circuit output via the 21st AND gate A ₂₁ which is in the open state by the 5th RS flip-flop output is
4th RS flip-flop FF ₄ in reset state
The 17th AND gate A ₁₇
At the same time as opening the _Y1 detection output, the 5th RS
The flip-flop _FF5 is reset and the seventh counter _CT7 is cleared again. The 7th cleared
The counter _CT7 starts counting the horizontal synchronizing signal H again, and only when the count value _Y2 is detected, the _Y2 detection circuit output resets the fourth RS flip-flop _FF4 and closes the seventeenth AND gate _A17. state. Therefore, in the first count starting from the input of the vertical synchronizing signal V, even if _Y2 is detected, the first count in the reset state is
There is no change in the output just by resetting the 4RS flip-flop FF ₄ , and even if _Y1 is detected in the later counting, the 21st AND gate A ₂₁ , which is closed by the 5th RS flip-flop FF ₅ , closes the 4th RS flip-flop. Reset output to FF ₄ is blocked, and no malfunction will occur regardless of the magnitude of the designated count value. Note that the 8th counter in Figure 8
_CT8 is connected to the seventh counter _CT7 , and the sixth RS flip-flop _FF6 is connected to the fifth RS flip-flop _FF5.
In addition, the seventh RS flip-flop FF ₇ is connected to the fourth RS flip-flop FF ₄ , and the X ₂ detection circuit CX ₂ is connected to the Y ₂
The _X1 detection circuit _CX1 is connected to the _Y1 detection circuit _CY1 , the 22nd AND gate _A22 is connected to _the 21st AND gate _A21 , and the third OR gate _O3 is connected to the second OR gate _O2. , respectively, and there is no difference in circuit operation just by setting the designated count values to X ₁ and X ₂ .

A circuit for generating a write pulse W for transferring the contents of the buffer memory and writing to a predetermined location in the main memory MM will be further explained below.
First, the first comparison circuit CF ₁ is a first X binary counter CT ₁ for specifying the position in the X _-axis direction in FIG.
and a second counter that counts the shift pulse G to the main memory MM and displays the scanning position of the television receiver in the X-axis direction,
When the count values of the first and second counters CT ₁ and CT ₂ match, an output is generated.

The first counter _CT1 has an output of a negation circuit N that inverts the output of a differentiating circuit DF that captures the falling part of the shift register output and generates a pulse;
An eleventh circuit that detects coincidence of the second monostable monomulti MO ₂ output triggered by the second frequency divider circuit DV ₂ that divides the write pulse W by 1/16 and detects the end of writing of the digital signal group B. The output of AND gate A ₁₁ is counted. For example, three rows or horizontal scan lines 48
If you wish to display the data for the entire purpose, the shift register output will go down after the end of writing of the third digital signal group is detected, and the X-axis direction specification will be displayed until all 48 digital signals have been stored. The 48 digital signals are stored in a continuous line in the Y-axis direction without changing their positions. Next, the second comparator circuit CF ₂ compares the count value of the third counter CT ₃ that counts the shift output to the shift register SR while being cleared by the falling edge of the shift register output, and 1/1 of the write pulse.
The purpose is to count the outputs divided by 16 and compare the count value of the fourth counter _CT4 , which is cleared by the eleventh AND gate output _A11 , to detect a match. The third counter _CT3 uses the shift register SR to specify the number of stages to increase when the display width is increased to multiple stages.
The fourth counter _CT4 counts the shift pulses input to the shift register SR and is cleared at the falling edge of the display signal U derived from the shift register SR. This is a counter that is cleared by the output of the eleventh AND gate _A11 , which generates an output every time it detects the end of storage in the width direction of the display line while counting the groups. Furthermore, the third comparison circuit CF ₃ is a shift register SR.
A sixth counter counts the output of the fifth counter _CT5 which is cleared by the vertical synchronizing signal V, and the output generated when the first counter _CT1 counts _X2 . This is a comparison circuit for specifying a display line that detects a match between the outputs of the counter _CT6 and generates an output. The sixth counter CT ₆ counts the output generated by the first counter upon detecting the end of the line in order to count the lines that have been stored, and specifies the _line to be stored. The number of display lines is counted based on the display output of the shift register SR, which is shifted in conjunction with the display position on the digital receiver.

Therefore, the first, second and third comparison circuits CF ₁ ,
A 12th AND gate that takes the AND of the matching outputs of CF ₂ and CF ₃ and the output of the third flip-flop FF ₃ , which is set upon completion of inputting the digital signal group to the buffer memory and reset upon completion of transfer.
A write pulse can be obtained from _A12 .

The following or further the first buffer memory BM ₁ and the second buffer memory BM 1 .
Shift pulse S ₁ input to buffer memory BM ₂ ,
I will explain about S ₂ . The buffer memory requires a delay pulse S related to the sub-pilot signal SP at the time of input, and a write shift pulse W at the time of transfer, so the shift pulse must be switched.
Such switching is performed by the 13th to 16th AND gates A ₁₃ , A ₁₄ ,
It is done by A ₁₅ and A ₁₆ . For example, if the Q of the second flip-flop FF ₂ output is “1” and “0”,
The second AND gate A ₁ and the third AND gate A ₃ , the 13th AND gate A ₁₃ and the 15th AND gate A ₁₅ in the pulse control circuit are respectively closed, and the second AND gate A ₂ is connected to the second buffer memory BM. ₂ into the input state, the third AND gate _A3 puts the first buffer memory BM1 into the transfer state, and the 13th AND gate A3 puts the first buffer memory _BM1 into the transfer state.
_A1 inputs a write shift pulse W to the first buffer memory _BM1 , and a fifteenth AND gate _A15 inputs a delay pulse S to the second buffer memory _BM2 . Therefore, the delay pulse S associated with the sub-pilot signal SP is input to the second buffer memory _BM2 to which the digital signal group B is input, and the write pulse W is input to the first buffer memory _BM1 on the transfer side.

On the other hand, the first flip-flop output R, which is inverted based on the detection output of the control signal, is connected to the second differentiator circuit.
It is input to DF ₂ and converted into a clear pulse M synchronized with the rising edge of the flip-flop output R, which is then applied to the first and second buffer memories BM ₁ and BM ₂ and the main memory.
Delete the memory contents of MM. In addition, the output X of the 19th AND gate that detects the coincidence output of the first and second gate controls BX ₁ and BX ₂ and the 10th AND gate A ₁₀ generates an output only during the display period, and the 7th AND gate is in an open state. Make it. Furthermore, the shift pulse G input to the main memory MM is changed to the first one in order to generate an output only for display.
20 and gate a ₂₀ by 10th and gate a ₁₀
The AND output of the output of the 18th AND gate _A18 and the output of the 18th AND gate A18 is used as a shift pulse.

The pulse control circuit PG configured as described above detects a control signal, clears the buffer memory BM and the main memory MM, then stores the display signal U, and the digital signal group B input following the display signal U is the delayed pulse S. The signal is input to the buffer memory on the input side. Main memory MM generated in connection with the scanning position of the television receiver TV and the display signal U
A shift pulse G to shift the contents of main memory MM to the sixth
Through the AND gate A ₆ , the television receiver is shifted cyclically and through the seventh AND gate A ₇ .
A write pulse W is input to the TV, and at the same time, a digital signal D is stored in a predetermined storage position of the main memory MM based on the display signal U and the count value of the write pulse W.
At this point, the fifth AND gate A ₅ is opened and the sixth AND gate A ₆ is closed, and a shift pulse for transfer generated simultaneously with the write pulse W causes the data to be stored in the main memory MM.

The video signal derived from the seventh AND gate _A7 by the above operation is connected to the video signal conversion circuit VM.
Through the RF conversion circuit RF, the television receiver TV
input to the antenna terminal.

Video signal VI played from tape recorder TR
When the first retriggerable monomulti RM ₁ generates an output upon detecting the end of the first flip-flop
FF ₁ is inverted, the switching circuit CH is switched to the audio circuit, and the audio signal AU following the video signal VI is sent to the audio amplifier.
After being amplified by 2 to AA, the video signal is sent to the high frequency conversion circuit RF.
It is configured to perform RF conversion along with the VI.

The gate control circuit of the present invention includes a pulse counting circuit, a first detection circuit that detects when the counting output reaches a predetermined first counting value, and a pulse counting circuit that detects when the counting output reaches the first counting value. a second detection circuit that detects when a second count value different from the first detection circuit is reached; a first flip-flop that is set by the operation start pulse and reset by the output of the first detection circuit; an AND gate that is opened by the output of the flop and derives the output of the first detection circuit;
It consists of an OR gate that applies the gate output and the operation start pulse as a clear signal to the counting circuit, and a second flip-flop that is set by the output of the AND gate and reset by the output of the second detection circuit. , the output of the second flip-flop is used as an opening/closing signal for an external gate. Therefore, it is only necessary to use one counting circuit with a number of bits that can count up to the larger of the first and second count values, and therefore, as in the conventional case, it is sufficient to use one counting circuit. 1.Use two counting circuits each capable of counting up to the second count value, or
Compared to configuring a similar gate control circuit using a counting circuit that can count up to the sum of the second count values, the number of required counting circuits or the number of digits can be reduced, resulting in lower cost. realizable.

[Brief explanation of the drawing]

The figures are diagrams showing one embodiment of the present invention,
Fig. 1 is a diagram explaining the contents of the video signal, Fig. 2 is a diagram explaining the content of the display signal, Fig. 3 is a diagram showing the display position on the display screen of the television receiver, and Fig. 4 is a diagram explaining the content of the display signal. , a schematic block diagram of the device of this embodiment,
FIG. 5 is a diagram showing the conversion state of input signals;
6 is a block diagram showing the pulse control circuit in the block diagram of FIG. 4, FIG. 7 is a block diagram of the first gate control circuit, FIG. 8 is a block diagram of the second gate control circuit,
Reveal each. Explanation of main drawing numbers, FF ₄ , FF ₅ , FF ₆ , FF ₇ ...
4th, 5th, 6th, 7th RS flip-flop,
CY ₁ ...Y ₁ detection circuit, CY ₂ ...Y ₂ detection circuit, CX ₁
...X ₁ detection circuit, CX ₂ ...X ₂ detection circuit, CT ₇ ,
CT ₈ ... 7th and 8th counter.

Claims (1)

[Scope of utility model registration request] Pulse counting circuits CT7 and CT8, first detection circuits CY ₁ and CX ₁ that detect when the counting output reaches a predetermined first count value, and Second detection circuit CY ₂ , CX ₂ that detects when a second count value different from the numerical value is reached
and the first flip-flop, which is set by the operation start pulse and reset by the output of the first detection circuit.
Flops FF ₅ and FF ₆ , AND gates A ₂₁ and A ₂₂ which are opened by the output of these flip-flops and derive the output of the first detection circuit, and the AND gate output and the operation start pulse are used for the counting. OR gate O ₂ applied as a clear signal of the circuit,
O ₃ and second flip-flops FF ₄ and FF ₇ which are set by the output of the AND gate and reset by the output of the second detection circuit, and the output of the second flip-flop is connected to an external gate. A gate control circuit designed to be used as an opening/closing signal.