KR940020583A

KR940020583A - Thin film transistor and its manufacturing method

Info

Publication number: KR940020583A
Application number: KR1019930001502A
Authority: KR
Inventors: 이원상
Original assignee: 이헌조; 주식회사 금성사
Priority date: 1993-02-04
Filing date: 1993-02-04
Publication date: 1994-09-16

Abstract

본 발명은 박막트랜지스터 및 그 제조방법에 관한 것으로, 종래 박막트랜지스터 제조에 있어 브레이크다운 전압을 높이기 위해 리세스 에칭시 리세스 식각액의 비율 제조 또는 식각액을 다르게 하여 리세스 구조를 변화시킴으로서 도핑층과 게이트 사이의 거리를 띄우거나 더블 리세스 구조를 갖도록 하였다.The present invention relates to a thin film transistor and a method for manufacturing the same. In the conventional thin film transistor manufacturing, the doping layer and the gate are changed by changing the recess structure by changing the ratio of the recess etchant or the etching solution in order to increase the breakdown voltage. To increase the distance between the two or have a double recess structure.

그러나, 이때 잔류된 도핑층이 적어짐에 따라 소오스와 드레인의 저항이 늘어나는 문제점과 더블리세스 에칭과 같은 복합한 공정을 수행해야 하는 문제점이 있었다.However, at this time, as the remaining doping layer decreases, there are problems in that the resistance of the source and drain increases and a complex process such as double recess etching is required.

본 발명은 이러한 문제점을 해결하기 위하여 활성층은 적게 드러나는 동시에 도핑층이 많이 잔류하는 리세스 에칭을 수행하고 리세스 에칭된 부분에 진공상태의 공간을 형성하여 브레이크다운 전압은 높아지고, 소오스와 게이트 사이의 저항은 줄일 수 있도록 하여 박막트랜지스터의 특성을 향상시키도록 하는 것이다.In order to solve this problem, the present invention performs a recess etch in which the active layer is less exposed and a large amount of the doping layer remains, and a vacuum space is formed in the recess etched portion to increase the breakdown voltage. The resistance can be reduced to improve the characteristics of the thin film transistor.

Description

Thin film transistor and its manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명 박막트랜지스터 구조도,4 is a structural diagram of a thin film transistor of the present invention,

제5도의 (가) 내지 (라)는 본 발명 박막트랜지스터 제조공정도.Figure 5 (a) to (d) is a manufacturing process diagram of the thin film transistor of the present invention.

Claims

A buffer layer 2, an active layer 3, and a doping layer 4 are successively formed on the silicon substrate 1 in a mesa shape, and the recessed etching is performed after the doping layer 4 and the active layer 3 are recess etched. A thin film transistor having a gate metal (6) formed at a portion thereof, wherein the space (20) in a vacuum state is formed between the active layer (3) and the gate electrode (6).

Successively depositing a buffer layer (2), an active layer (3), a doping layer (4) on the silicon substrate (1), and then mesa etching to form a source-drain electrode (5), and the source-drain electrode (5). Depositing and then etching the insulating film 7 on the insulating layer; depositing metal to form the gate electrode 6 and the vacuum space 20 in the recessed portion; And depositing an insulating film 11 on the gate electrode 6 after the lift-off process, and forming a pad 8 on the etched portion after etching the insulating film 11. Thin film transistor manufacturing method.

The method of claim 2, wherein the etching is performed by using an insulating film (7) during the recess etching.

4. A method according to claim 3, wherein the recess etch etches so that the active layer (3) is less exposed and the doping layer (4) remains.

※ Note: The disclosure is based on the initial application.