KR950015661A - Manufacturing Method of Thin Film Transistor - Google Patents

Manufacturing Method of Thin Film Transistor Download PDF

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Publication number
KR950015661A
KR950015661A KR1019930023068A KR930023068A KR950015661A KR 950015661 A KR950015661 A KR 950015661A KR 1019930023068 A KR1019930023068 A KR 1019930023068A KR 930023068 A KR930023068 A KR 930023068A KR 950015661 A KR950015661 A KR 950015661A
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KR
South Korea
Prior art keywords
manufacturing
current
channel
thin film
film transistor
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Application number
KR1019930023068A
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Korean (ko)
Other versions
KR100261680B1 (en
Inventor
이현우
우상호
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019930023068A priority Critical patent/KR100261680B1/en
Publication of KR950015661A publication Critical patent/KR950015661A/en
Application granted granted Critical
Publication of KR100261680B1 publication Critical patent/KR100261680B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

본 발명은 LCD나 에스램 등에 사용되는 TFT의 제조 방법에 관한 것으로서, a-Si을 두껍게 형성한 후, 저온에서 장시간 열처리하여 그레인 바운더리가 큰 폴리 실리콘 층을 형성하고, 상기 폴리 실리콘층을 에치백하여 TFT에 적당한 두께로 식각하여 채널 폴리를 형성하였으므로, 두꺼운 채널의 장점인 높은 온전류, 낮은 오프전류, 작은 스윙 폭등의 특성에 의해 LCD응용시에는 콘트라스트가 증가되고, 소비전력이 감소되며, 소자의 동작 속도가 증가되는 효과가 있으며, 에스램 적용시에는 소비 전력 감소 및 온 전류 증가에 의해 소프트 에러율이 감소된다.The present invention relates to a method for manufacturing a TFT used in an LCD, an SRAM, etc., wherein a-Si is thickly formed and then heat-treated at a low temperature for a long time to form a large grain boundary polysilicon layer, and the polysilicon layer is etched back. Since the channel poly is formed by etching to a suitable thickness on the TFT, the contrast is increased and the power consumption is reduced in LCD applications due to the characteristics of the thick channel, such as high on current, low off current, and small swing width. In addition, the operating speed is increased, and in the application of SRAM, the soft error rate is reduced by reducing power consumption and increasing on current.

Description

박막 트랜지스터의 제조방법Manufacturing Method of Thin Film Transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 (A)~(D)는 본 발명의 일실시예에 따른 박막트랜지스터의 제조 공정도,1 (A) to (D) is a manufacturing process diagram of a thin film transistor according to an embodiment of the present invention,

제2도는 (A)~(C)는 본 발명의 다른 실시예에 따른 박막트랜지스터의 제조 공정도.2 is a manufacturing process diagram of a thin film transistor according to another embodiment of the present invention (A) ~ (C).

Claims (4)

절연기판상에 형성되는 박막 트랜지스터의 제조 방법에 있어서, 박막 트랜지스터의 채널층으로 사용될 비정질 실리콘층을 채널층의 두께보다 두껍게 형성하는 공정과, 상기 비정질 실리콘층을 소정온도에서 소정시간 동안 열처리하여 그레인 바운더리가 성장된 폴리 실리콘층을 형성하는 공정과, 상기 폴리 실리콘층을 소정 두께 제거하여 채널 폴리를 형성하는 공정을 포함하는 박막 트랜지스터의 제조 방법.A method of manufacturing a thin film transistor formed on an insulating substrate, comprising: forming an amorphous silicon layer to be used as a channel layer of a thin film transistor thicker than a channel layer, and heat-treating the amorphous silicon layer at a predetermined temperature for a predetermined time to obtain grain. And forming a channel poly by removing a predetermined thickness of the polysilicon layer. 제1항에 있어서, 상기 비정질 실리콘층을 1500~3000Å정도의 두께로 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조 방법.The method of claim 1, wherein the amorphous silicon layer is formed to a thickness of about 1500 to 3000 kPa. 제1항에 있어서, 상기 비정질 실리콘층을 580~650Å에서 2~24시간 열처리하는 것을 특징으로 하는 박막 트랜지스터의 제조 방법.The method of claim 1, wherein the amorphous silicon layer is heat-treated at 580 to 650 kPa for 2 to 24 hours. 제1항에 있어서, 상기 채널 폴리의 두께가 200~800Å정도가 되도록 식각하는 것을 특징으로 하는 박막 트랜지스터의 제조 방법.The method of claim 1, wherein the channel poly is etched to have a thickness of about 200 to about 800 μs. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930023068A 1993-11-02 1993-11-02 Method for fabricating thin film transistor KR100261680B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930023068A KR100261680B1 (en) 1993-11-02 1993-11-02 Method for fabricating thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930023068A KR100261680B1 (en) 1993-11-02 1993-11-02 Method for fabricating thin film transistor

Publications (2)

Publication Number Publication Date
KR950015661A true KR950015661A (en) 1995-06-17
KR100261680B1 KR100261680B1 (en) 2000-07-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930023068A KR100261680B1 (en) 1993-11-02 1993-11-02 Method for fabricating thin film transistor

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100362187B1 (en) * 1995-12-28 2003-03-06 주식회사 하이닉스반도체 Method for manufacturing thin film transistor
KR100428782B1 (en) * 2001-04-11 2004-04-27 삼성전자주식회사 Apparatus for measuring tension of pogo pin

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100362187B1 (en) * 1995-12-28 2003-03-06 주식회사 하이닉스반도체 Method for manufacturing thin film transistor
KR100428782B1 (en) * 2001-04-11 2004-04-27 삼성전자주식회사 Apparatus for measuring tension of pogo pin

Also Published As

Publication number Publication date
KR100261680B1 (en) 2000-07-15

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