KR940020233A - Dynamic RAM Memory (DRAM) Access Control - Google Patents

Dynamic RAM Memory (DRAM) Access Control Download PDF

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Publication number
KR940020233A
KR940020233A KR1019930001474A KR930001474A KR940020233A KR 940020233 A KR940020233 A KR 940020233A KR 1019930001474 A KR1019930001474 A KR 1019930001474A KR 930001474 A KR930001474 A KR 930001474A KR 940020233 A KR940020233 A KR 940020233A
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KR
South Korea
Prior art keywords
memory
dram
dynamic ram
access
ram memory
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Application number
KR1019930001474A
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Korean (ko)
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KR950008663B1 (en
Inventor
인희식
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이헌조
주식회사 금성사
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Priority to KR1019930001474A priority Critical patent/KR950008663B1/en
Publication of KR940020233A publication Critical patent/KR940020233A/en
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Publication of KR950008663B1 publication Critical patent/KR950008663B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)

Abstract

본 발명은 다이나믹 램 메모리(DRAM)를 사용하는 컴퓨터 시스템에서 다이나믹 램 메모리(DRAM)를 액세스 제어하는 장치에 관한 것으로 특히 인터리브 메모리 모드(INTERLEAVED MEMORY MODE)에서 메모리 제어 효율을 높일 수 있도록 한 다이나믹 램 메모리(DRAM)의 액세스 제어장치에 관한 것이다.The present invention relates to an apparatus for access control of a dynamic RAM memory (DRAM) in a computer system using the dynamic RAM memory (DRAM), and in particular, a dynamic RAM memory for improving memory control efficiency in an interleaved memory mode (INTERLEAVED MEMORY MODE). (DRAM) relates to an access control device.

종래의 다이나믹 램 메모리(DRAM) 액세스 장치에 의하면 메모리 액세스가 시이퀀셜하게 이루어지기 때문에 뱅크를 분리하여 설계한 효과가 제한적이고, 메모리를 액세스하는 프로그램은 대부분 연속적인 어드레스를 사용하는데 비하여 종래의 회로는 뱅크별로 묶어서 메모리 제어신호를 드라이브하기 때문에 다이나믹 램 메모리(DRAM)의 리드 시간이 길어지게 되어 시스템 성능이 저하되는 문제점이 있다.According to the conventional dynamic RAM memory (DRAM) access device, since the memory access is made sequentially, the effect of designing the banks separately is limited, and the program that accesses the memory mostly uses consecutive addresses. Since the memory control signals are grouped by banks, the read time of the dynamic RAM memory (DRAM) becomes long, thereby degrading system performance.

본 발명은 메모리의 액세스(리드)시에 시이퀀셜 액세스의 경우 미리 인접한 메모리를 원하는 데이터 액세스와 함께 동시에 액세스하여 래치하여 두고 이를 연속적인 다음 어드레스 드라이브시에 출력해 주므로서 메모리 액세스 효율을 높이고 이에 따른 시스템의 성능 향상을 기할 수 있도록 한 것으로 다이나믹 램 메모리(DRAM) 액세스 제어장치에 적용한다.In the case of sequential access during memory access (lead), the present invention improves memory access efficiency by simultaneously accessing and latching adjacent memories simultaneously with desired data access and outputting them at successive next address drives. It is used to improve the performance of the system and is applied to the dynamic RAM memory (DRAM) access control device.

Description

다이나믹 램 메모리(DRAM) 액세스 제어장치Dynamic RAM Memory (DRAM) Access Control

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 다이나믹 램 메모리(DRAM) 액세스 제어장치의 블록 구성도.3 is a block diagram of a dynamic RAM memory (DRAM) access control device of the present invention.

제4도는 다이나믹 램 메모리(DRAM) 액세스 제어장치에서 메모리 제어로직부의 로직 구성을 나타낸 도표(BOOLEAN EQUATION).4 is a diagram illustrating a logic configuration of a memory control logic unit in a dynamic RAM memory (DRAM) access control apparatus (BOOLEAN EQUATION).

Claims (1)

데이터의 저장 및 해독이 이루어지는 메모리 뱅크(6,7)와, 상기 메모리 뱅크의 데이터 출력을 위한 버퍼(8,9)와, 상기 메모리 뱅크의 시이퀀셜한 다음 어드레스 데이터가 저장되어 출력되는 래치(10,11)와, 어드레스(Addr), 램선택신호(/RAMSEL) 라이트 인에이블신호(/WE)를 입력함으로 하여 상기 메모리 뱅크(6,7)를 모두 액세스 시작하고 첫 번째 요구된 뱅크의 데이터를 상기 버퍼(8,9)를 통해 전송하고 그 다음 어드레스의 데이터는 래치(10,11)에 저장하였다가 다음 메모리 액세스 시에 상기 래치 데이터를 출력 제어하는 메모리 제어 로직부(12)로 구성된 다이나믹 램 메모리(DRAM) 액세스 제어장치.Memory banks 6 and 7 in which data is stored and decoded, buffers 8 and 9 for data output of the memory banks, and latches 10 in which the sequential address data of the memory banks are stored and outputted. (11), the address (Addr) and the RAM select signal (/ RAMSEL) write enable signal (/ WE) are inputted to start accessing all of the memory banks 6 and 7, and the data of the first requested bank is started. Dynamic RAM comprising a memory control logic section 12 which transfers through the buffers 8 and 9 and stores the data of the next address in the latches 10 and 11 and outputs the latch data upon the next memory access. Memory (DRAM) access control. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930001474A 1993-02-04 1993-02-04 Dram access control apparatus KR950008663B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930001474A KR950008663B1 (en) 1993-02-04 1993-02-04 Dram access control apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930001474A KR950008663B1 (en) 1993-02-04 1993-02-04 Dram access control apparatus

Publications (2)

Publication Number Publication Date
KR940020233A true KR940020233A (en) 1994-09-15
KR950008663B1 KR950008663B1 (en) 1995-08-04

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Application Number Title Priority Date Filing Date
KR1019930001474A KR950008663B1 (en) 1993-02-04 1993-02-04 Dram access control apparatus

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KR950008663B1 (en) 1995-08-04

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