KR940016906A - Manufacturing method of LED NMOS MOS transistor - Google Patents

Manufacturing method of LED NMOS MOS transistor Download PDF

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Publication number
KR940016906A
KR940016906A KR1019920025337A KR920025337A KR940016906A KR 940016906 A KR940016906 A KR 940016906A KR 1019920025337 A KR1019920025337 A KR 1019920025337A KR 920025337 A KR920025337 A KR 920025337A KR 940016906 A KR940016906 A KR 940016906A
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South Korea
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manufacturing
region
oxide film
mos transistor
led
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KR1019920025337A
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Korean (ko)
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KR950008260B1 (en
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유종선
백종태
남기수
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양승택
재단법인 한국전자통신연구소
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 엘디디 엔채널 모스 트랜지스터의 제조방법에 관한 것으로, 소오스와 드레인의 두 엘디디영역(39)은 게이트와의 중첩이 완전히 대칭적이며 펀치드루우 전압을 높이기 위한 P-영역(38)은 소오스와 드레인의 채널쪽부분에만 좁게 형성되어 있되, 엘디디영역(39)과 P-영역(38)이 각각 PSG로부터 확산되는 인(P)과 BSG로부터 확산되는 붕소(B)에 의해 형성되는 것이 특징이다.The present invention relates to a method for manufacturing an LED NMOS MOS transistor, wherein the two LED regions 39 of the source and drain are completely symmetrical with their gates, and have a P − region 38 for increasing the punch draw voltage. Is narrowly formed only at the channel side of the source and drain, and the LED region 39 and the P − region 38 are formed by phosphorus (P) diffused from the PSG and boron (B) diffused from the BSG, respectively. Is characteristic.

Description

엘디디 엔채널 모스 트랜지스터의 제조방법Manufacturing method of LED NMOS MOS transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 4 도 (가) 내지 (아)는 본 발명에 의한 엘디디 모스 트랜지스터 구조의 제조공정단면도.4 (a) to (h) are sectional views of the manufacturing process of the LED transistor structure according to the present invention.

Claims (7)

규소기판(1) 위에 필드산화막(2)과 게이트(28) 및 게이트산화막(27)을 순차로 형성하여 모스트랜지스터를 제조하는 방법에 있어서, 열산화에 의해 웨이퍼 표면에 소정의 두께로 규소산화막(29)을 형성하는 단계와, LPCVD에 의해 BSG(boro-silica-glass)를 형성하고 식각하여 상기 게이트(28)의 측면에 측벽산화막(30)을 형성하는 단계와, 상기 측벽산화막(3)을 이루는 상기 BSG에 함유된 붕소를 상기 규소기판(1)속으로 열확산시켜 P-영역(31)을 형성하는 단계와, 상기 규소산화막(29)을 습식식각한후 상기 LPCVD에 의해 30 내지 100nm의 두께로 PSG(phospho-silica-glass)(33)를 형성하는 단계와, 상기 PSG(33)에 함유된 인을 상기 규소기판(1)속으로 열확산시켜 n-영역(35)을 형성하는 단계와, 비소를 이온주입한후 엘디디(39)와 소오스(40) 및 드레인(41)을 형성하는 단계를 포함하는 것을 특징으로 하는 엘디디 엔채널 모스 트랜지스터의 제조방법.In the method of manufacturing the MOS transistor by sequentially forming the field oxide film 2, the gate 28, and the gate oxide film 27 on the silicon substrate 1, the silicon oxide film (with a predetermined thickness on the wafer surface by thermal oxidation) 29), forming a boro-silica-glass (BSG) by LPCVD and etching to form a sidewall oxide film 30 on the side of the gate 28, and the sidewall oxide film 3 Forming a P − region 31 by thermally diffusing boron contained in the BSG into the silicon substrate 1, wet etching the silicon oxide layer 29, and performing a thickness of 30 to 100 nm by LPCVD. Forming a PSG (phospho-silica-glass) 33, thermally diffusing phosphorus contained in the PSG 33 into the silicon substrate 1 to form an n − region 35, And implanting the arsenic 39 and the source 40 and the drain 41 after ion implantation. A method for manufacturing an LED N-channel MOS transistor. 제 1 항에 있어서, 상기 규소산화막(29)은 100Å 내지 200Å 두께로 형성되고, 상기 PSG(33)는 30nm 내지 10nm의 두께로 형성되는 것을 특징으로 하는 엘디디 엔채널 모스 트랜지스터의 제조방법.The method of claim 1, wherein the silicon oxide film (29) is formed to a thickness of 100 kHz to 200 kHz, and the PSG (33) is formed to a thickness of 30 nm to 10 nm. 제 1 항에 있어서, 상기 측벽산화막(30)으로부터 상기 규소기판(1)내로 인을 확산시켜 상기 P-영역(31)을 형성하는 단계는 급속열처리와 열확산중 어느하나에 의해 수행되고, 상기 급속열처리는 1000℃ 내지 1050℃의 온도에서 30초 내지 2분동안 수행되고, 상기 열확산은 900℃ 내지 650℃의 온도에서 10분 내지 60분동안 수행되는 것을 특징으로 하는 엘디디 엔채널 모스 트랜지스터의 제조방법.The method of claim 1, wherein the forming of the P − region 31 by diffusing phosphorus from the sidewall oxide film 30 into the silicon substrate 1 is performed by either rapid thermal treatment or thermal diffusion. The heat treatment is performed for 30 seconds to 2 minutes at a temperature of 1000 ℃ to 1050 ℃, the thermal diffusion is carried out for 10 minutes to 60 minutes at a temperature of 900 ℃ to 650 ℃ to manufacture an LED NMOS transistor Way. 제 1 항에 있어서, 상기 PSG(33)에 의해 상기 n-영역(35)을 형성하는 단계는 급속열처리와 열확산중 어느하나에 의해 수행되고, 상기 급속열처리는 950℃ 내지 1050℃의 온도에서 10초 내지 60초 동안 수행되고, 상기 열확산은 850℃ 내지 900℃의 온도에서 10분 내지 30분동안 수행되는 것을 특징으로 하는 엘디디 엔채널 모스 트랜지스터의 제조방법.The method of claim 1, wherein the forming of the n − region 35 by the PSG 33 is performed by either rapid thermal treatment or thermal diffusion, and the rapid thermal treatment is performed at a temperature of 950 ° C. to 1050 ° C. 10. Second to 60 seconds, the thermal diffusion is a method for manufacturing an LED channel MOS transistor, characterized in that performed for 10 to 30 minutes at a temperature of 850 ℃ to 900 ℃. 제 1 항 도는 제 3 항에 있어서, 상기 P-영역(31)은 0.2 내지 0.4㎛의 깊이와 5×1016내지 1×1017㎝-3의 농도로 형성되는 것을 특징으로 하는 엘디디 엔채널 모스 트랜지스터의 제조방법.4. The LED channel of claim 1, wherein the P − region 31 is formed at a depth of 0.2 μm to 0.4 μm and a concentration of 5 × 10 16 to 1 × 10 17 cm −3 . Method of manufacturing MOS transistor. 제 1 항 도는 제 4 항에 있어서, 상기 n-영역(35)은 0.1 내지 0.2㎛의 깊이와 1×1017내지 5×1017㎝-3의 농도로 형성되는 것을 특징으로 하는 엘디디 엔채널 모스 트랜지스터의 제조방법.5. The LED channel of claim 1, wherein the n − region 35 is formed at a depth of 0.1 to 0.2 μm and a concentration of 1 × 10 17 to 5 × 10 17 cm −3 . Method of manufacturing MOS transistor. 제 1 항에 있어서, 상기 BSG와 상기 PSG는 SiH4와 O2가스분위기에서 희석된 BH3가스를 운반가스에 혼합하여 300 내지 500℃에서 열분해하는 것에 의해 각각 형성되는 것을 특징으로 하는 엘디디 엔채널 모스트랜지스터의 제조방법.The method of claim 1, wherein the BSG and the PSG are formed by mixing each of the BH 3 gas diluted in the SiH 4 and O 2 gas atmosphere in the carrier gas and pyrolysis at 300 to 500 ℃, respectively, Method of manufacturing channel morph transistors. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920025337A 1992-12-24 1992-12-24 Making method of ldd n-channel mos transistor KR950008260B1 (en)

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KR1019920025337A KR950008260B1 (en) 1992-12-24 1992-12-24 Making method of ldd n-channel mos transistor

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KR950008260B1 KR950008260B1 (en) 1995-07-26

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