JPS63302518A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63302518A JPS63302518A JP13939387A JP13939387A JPS63302518A JP S63302518 A JPS63302518 A JP S63302518A JP 13939387 A JP13939387 A JP 13939387A JP 13939387 A JP13939387 A JP 13939387A JP S63302518 A JPS63302518 A JP S63302518A
- Authority
- JP
- Japan
- Prior art keywords
- impurity
- conductivity type
- source
- region
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000012535 impurity Substances 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000007787 solid Substances 0.000 claims abstract 11
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 9
- 239000000758 substrate Substances 0.000 description 7
- 229910052785 arsenic Inorganic materials 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- -1 phosphorus ions Chemical class 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011505 plaster Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［概要］
一導電型不純物領域と異種導電型不純物領域とを同時に
画定する形成方法であって、一方を面体不純物源とし、
他方をガス不純物源とするか、あるいは、両方を面体不
純物源にして、上面からレーザを照射して両方の不純物
領域を同時に画定する。そうすれば、処理工程が節単に
なり、短縮されて、且つ、微細領域を高精度に形成でき
る。[Detailed Description of the Invention] [Summary] A formation method for simultaneously defining an impurity region of one conductivity type and an impurity region of a different conductivity type, in which one is used as a planar impurity source,
The other is used as a gas impurity source, or both are used as a surface impurity source, and both impurity regions are defined simultaneously by irradiating a laser from the top surface. In this way, the processing steps can be simplified and shortened, and fine regions can be formed with high precision.
［産業上の利用分野］
本発明は半導体装置の製造方法に係り、特に、２つの異
種導電型不純物領域を同゛時に形成する形成方法に関す
る。[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming two impurity regions of different conductivity types at the same time.
ＩＣやＬＳＩなどの半導体装置は複雑で長い処理工程か
らなるウェハープロセスを経て半導体チップが作製され
ている。Semiconductor chips of semiconductor devices such as ICs and LSIs are fabricated through a wafer process that includes complicated and long processing steps.
しかし、処理工程が長くなるほど、ハンドリング回数が
増加するために品質や収率（歩留）が低下し、また、工
数増加によるコストアップに繋がって、出来るだけ短縮
した簡略な処理工程による形成方法が望ましい。However, as the treatment process becomes longer, the quality and yield decrease due to the increased number of handling steps, and the cost increases due to the increase in man-hours. desirable.
［従来の技術］
第３図はＣ−ＭＯＳ）ランジスタ（相補型電界効果形ト
ランジスタ）の断面概要図を示しており、このようなＣ
−ＭＯＳ ）ランジスタは消費電力が少ない等の利点が
あって、広く利用されている構造である。図において、
１はｐ−シリコン基板（ｐ型不純物を含むシリコン基板
）、２はｎ−ウェル領域、３はフィールド絶縁膜（Ｓｉ
Ｏ２膜）、４は多結晶シリコン膜からなるゲート電極
、５はｎチャネルトランジスタのｎ−ソース領域および
ドレイン領域、６はｐチャネルトランジスタのｐ−ソー
ス領域およびドレイン領域である。[Prior Art] Figure 3 shows a schematic cross-sectional view of a C-MOS transistor (complementary field effect transistor).
-MOS) transistors have advantages such as low power consumption, and are a widely used structure. In the figure,
1 is a p-silicon substrate (silicon substrate containing p-type impurities), 2 is an n-well region, and 3 is a field insulating film (Si
4 is a gate electrode made of a polycrystalline silicon film, 5 is an n-source region and a drain region of an n-channel transistor, and 6 is a p-source region and a drain region of a p-channel transistor.
このようなＣ−ＭＯＳ）ランジスタの従来の形成方法の
工程順断面図を第４図（ａ）〜（Ｃ１に示している。Step-by-step sectional views of a conventional method for forming such a C-MOS transistor are shown in FIGS. 4(a) to (C1).
第４図（ａ）参照；ｐ−シリコン基板１上にｎ−ウェル
領域２を画定し、次いで、フィールド絶縁膜３を形成し
た後、ゲート絶縁膜を、介してゲート電極４を形成する
。Refer to FIG. 4(a); after an n-well region 2 is defined on a p-silicon substrate 1 and a field insulating film 3 is formed, a gate electrode 4 is formed via a gate insulating film.
第４図（ｂ）参照；次いで、ｎ−ウェル領域２ （ｐチ
ャネルトランジスタ形成領域）上にレジスト膜マスク７
を被覆し、露出させたｎチャーネルトランジスタ形成領
域上から燐イオン（ｐ＋）または砒素イオン（八Ｓ＋
）を注入し、熱処理してｎ−ソース領域およびドレイン
領域５を画定する。なお、この熱処理は、後記するｐチ
ャネルトランジスタのｐ−ソース領域およびドレイン領
域６をイオン注入した後、同時に熱処理して画定する場
合が多い。Refer to FIG. 4(b); Next, a resist film mask 7 is placed on the n-well region 2 (p-channel transistor formation region).
phosphorus ions (p+) or arsenic ions (8S+) from above the exposed n-channel transistor formation region.
) is implanted and heat treated to define n-source and drain regions 5. Note that this heat treatment is often performed at the same time after ion implantation into the p-source region and drain region 6 of a p-channel transistor to be described later.
第４図（Ｃ１参照；次いで、前工程で形成したｎチャネ
ルトランジスタ領域上にレジスト膜マスク８を被覆し、
ｐチャネルトランジスタ形成領域を露出させて、その上
から硼素イオン（Ｂ＋）を注入し、熱処理してｐ−ソー
ス領域およびドレイン領域６を画定する。FIG. 4 (see C1; next, a resist film mask 8 is coated on the n-channel transistor region formed in the previous step,
The p-channel transistor forming region is exposed, boron ions (B+) are implanted thereon, and a p- source region and drain region 6 are defined by heat treatment.
なお、これらのソースおよびドレイン領域の形成工程に
おいては、ゲート電極４およびフィールド絶縁膜３がイ
オン注入を防止するマスクの役目を果たし、セルファラ
イン（自己整合）的にソース・ドレイン領域が形成され
るものである。In the process of forming these source and drain regions, the gate electrode 4 and field insulating film 3 serve as a mask to prevent ion implantation, and the source and drain regions are formed in a self-aligned manner. It is something.
［発明が解決しようとする問題点］
ところで、上記のようなＣ−ＭＯＳ ）ランジスタのソ
ースおよびドレイン領域の形成工程はレジスト膜マスク
７．８を２回パターンニングし、２回に分けてイオン注
入する形成方法であるから、それだけ処理工程が長くな
って工数が増加する問題がある。[Problems to be Solved by the Invention] By the way, in the process of forming the source and drain regions of the C-MOS transistor as described above, the resist film mask 7.8 is patterned twice and ions are implanted in two steps. Therefore, there is a problem that the processing steps become longer and the number of man-hours increases accordingly.
且つ、従来のように、イオン注入によって形成する場合
は高温熱処理（９００〜１０００℃程度）が必要になる
ため、過度の熱拡散によって微細な領域を高精度に形成
できない欠点がある。Moreover, when forming by ion implantation as in the past, high temperature heat treatment (approximately 900 to 1000° C.) is required, which has the disadvantage that fine regions cannot be formed with high precision due to excessive thermal diffusion.
本発明はこのような問題点を除去して、ｎチャネルトラ
ンジスタのｎ−ソースおよびドレイン領域と、ｐチャネ
ルトランジスタのｐ−ソースおよびドレイン領域を同時
に形成し、しかも、熱処理が不要で高精度に、且つ、微
細に形成できる形成方法を提案するものである。The present invention eliminates these problems and simultaneously forms the n-source and drain regions of an n-channel transistor and the p-source and drain regions of a p-channel transistor, and moreover, with high precision without the need for heat treatment. Moreover, the present invention proposes a forming method that allows fine formation.
［問題点を解決するための手段］
その目的は、一導電型面体不純物源を一導電型不純物形
成領域上に配置し、且つ、異種導電型不純物ガスを含む
雰囲気中に異種導電型不純物形成領域を露出させ、全面
にレーザを照射して前記面体不純物源とガス不純物源と
から同時に拡散させて一導電型不純物領域と異種導電型
不純物領域とを画定する工程、あるいは、一導電型面体
不純物源を一導電型不純物形成領域上に配置し、且つ、
異種導電型面体不純物源を異種導電型不純物形成領域上
に配置し、全面にレーザを照射して前記２つの面体不純
物源から同時に拡散させて一導電型不純物領域と異種導
電型不純物領域とを画定する工程が含まれる半導体装置
の製造方法によって達成される。[Means for Solving the Problems] The purpose is to place a one-conductivity type impurity impurity source on one conductivity type impurity formation region, and to place a different conductivity type impurity formation region in an atmosphere containing a different conductivity type impurity gas. a step of exposing the entire surface and irradiating the entire surface with a laser to simultaneously diffuse from the surface impurity source and the gas impurity source to define an impurity region of one conductivity type and an impurity region of different conductivity type; is placed on the impurity formation region of one conductivity type, and
Plaster impurity sources of different conductivity types are placed on the impurity formation region of different conductivity types, and the entire surface is irradiated with a laser to simultaneously diffuse from the two plane impurity sources to define an impurity region of one conductivity type and an impurity region of different conductivity types. This is achieved by a method of manufacturing a semiconductor device that includes the steps of:
［作用］
即ち、本発明は、一導電型不純物領域と異種導電型不純
物領域とを同時に形成するために、一方を面体不純物源
にし、他方をガス不純物源にする方法、または、両方を
面体不純物源にする方法によって不純物源を準備し、そ
の上からレーザを照射し拡散させて不純物領域を同時に
画定する。[Operation] That is, the present invention provides a method in which one conductivity type impurity region and a different conductivity type impurity region are formed simultaneously by using a method in which one is made into a faceted impurity source and the other is made into a gaseous impurity source, or both are made into a faceted impurity source. An impurity source is prepared by a method using a source, and a laser is irradiated and diffused from above to simultaneously define an impurity region.
そうすれば、パターンニングも１回だけになり、処理工
程が簡略になって、短縮され、しかも、微細な領域を精
度良く形成することができる。In this way, patterning is performed only once, the processing steps are simplified and shortened, and fine regions can be formed with high precision.
［実施例］ 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.
第１図（ａ）、 （ｂ）は本発明にかかる形成方法を示
す工程順断面図である。FIGS. 1(a) and 1(b) are step-by-step sectional views showing the forming method according to the present invention.
第１図（ａ）参照；本図は従来例の第４図（ａ）と同様
に、ｐ−シリコン基板１上にｎ−ウェル領域２を画定し
、次いで、フィールド絶縁膜３を形成し、次いで、ゲー
ト絶縁膜を介してゲート電極４を形成する。Refer to FIG. 1(a); In this figure, similarly to FIG. 4(a) of the conventional example, an n-well region 2 is defined on a p-silicon substrate 1, and then a field insulating film 3 is formed. Next, a gate electrode 4 is formed via a gate insulating film.
第１図中）参照；次いで、砒素１２％含んだ膜厚３００
０人程度０砒素シリケートガラス（ＡｓＳＧ）膜（ｎ型
不純物源）を上面に被着し、これをフォトプロセスによ
ってパターンニングしてｎチャネルトランジスタ形成領
域上のみをＡｓ５Ｇ膜１０で被覆し、次いで、ジボラン
（８２Ｈ６）ガス雰囲気の減圧気中（１０Ｔｏｒｒ）に
おいて、エキシマレーザ（Ａｒ Ｆレーザ）でスキャン
ニングしながら１秒間照射する。この際、基板は加熱せ
ず、レーザ照射による熱量は２〜１０ジユ一ル／ｃｄ程
度、波長１１Ｚの１パルスで各部分を１回照射するだけ
である。なお、ジボランガス雰囲気はキャリアガスをア
ルゴンとした１％の８２ Ｈ６ガスを含んだ雰囲気であ
る。(See Figure 1); Next, a film with a thickness of 300 containing 12% arsenic was prepared.
An arsenic silicate glass (AsSG) film (n-type impurity source) was deposited on the top surface, and this was patterned by a photo process to cover only the n-channel transistor formation region with an As5G film 10. Then, Irradiation is performed for 1 second while scanning with an excimer laser (Ar F laser) in a reduced pressure (10 Torr) of diborane (82H6) gas atmosphere. At this time, the substrate is not heated, the amount of heat by laser irradiation is about 2 to 10 J/cd, and each part is irradiated only once with one pulse of wavelength 11Z. Note that the diborane gas atmosphere is an atmosphere containing 1% 82 H6 gas with argon as a carrier gas.
そうすれば、このレーザ照射によってｎチャネルトラン
ジスタのｎ−ソース領域沿よびドレイン領域１５がＡｓ
５Ｇ膜１０からの拡散によって形成され、又、ｐチャネ
ルトランジスタのｐ−ソース領域およびドレイン領域１
６はＢ２ Ｈ６ガスからの拡散によって同時に形成され
、しかも、これらのソース・ドレイン領域は厚さ１００
０人程度人程めて？１１１１Ｉで高精度に形成すること
ができる。Then, by this laser irradiation, the area along the n-source region and the drain region 15 of the n-channel transistor becomes As.
It is formed by diffusion from the 5G film 10, and also forms the p- source region and drain region 1 of the p-channel transistor.
6 are simultaneously formed by diffusion from B2 H6 gas, and these source and drain regions have a thickness of 100 mm.
Approximately 0 people? 1111I can be formed with high precision.
次に、第２図＋８）、 （ｂ）は本発明にかかる他の形
成方法を示す工程順断面図である。Next, FIG. 2+8) and (b) are step-by-step sectional views showing another forming method according to the present invention.
第２図（ａ）参照；本図も従来例の第４図（ａ）と同じ
く、ｐ−シリコン基板１上にｎ−ウェル領域２を画定し
、次いで、フィールド絶縁膜３を形成し、次いで、ゲー
ト絶縁膜を介してゲート電極４を形成する。Refer to FIG. 2(a); In this figure, similarly to the conventional example shown in FIG. 4(a), an n-well region 2 is defined on a p-silicon substrate 1, a field insulating film 3 is formed, and then , a gate electrode 4 is formed via a gate insulating film.
第２図（ｂｌ参照；次いヤ、砒素１２％含んだ膜厚３０
００人程度０砒素シリケートガラス（ＡｓＳＧ）膜を上
面に被着し、これをフォトプロセスによってパターンニ
ングして、ｎチャネルトランジスタ形成領域上のみをＡ
ｓ５Ｇ膜１０で被覆し、次いで、その上に硼素１２％含
んだ膜厚３０００人の硼素シリケートガラＸ（ＢＳＣ；
）膜（ｐ型不純物源）を被着して、ｐチャネルトランジ
スタ形成領域上をＢＳＧ膜１１で被覆した後、上記例と
同様にエキシマレーザ（ＡｒＦレーザ）でスキャンニン
グしながら１秒間照射する。その時のレーザ照射の条件
は上記と同様である。そうすれば、このレーザ照射によ
ってｎチャネルトランジスタのｎ−ソース領域およびド
レイン領域１５が＾ｓＳＧ膜１０からの拡散によって形
成され′、又、ｐチャネルトランジスタのｐ−ソース領
域およびドレイン領域１６がＢＳＧ膜１１がらの拡散に
よって同時に形成されて、しかも、これらの領域は極め
て微細で高精度に形成される。Figure 2 (see BL; next, film thickness 30% containing 12% arsenic)
An arsenic silicate glass (AsSG) film is deposited on the top surface and patterned by a photo process to form an arsenic silicate glass (AsSG) film only on the n-channel transistor formation region.
It was coated with s5G film 10, and then coated with 3000% boron silicate gala X (BSC) containing 12% boron.
) film (p-type impurity source) to cover the p-channel transistor formation region with the BSG film 11, and then irradiation is performed for 1 second while scanning with an excimer laser (ArF laser) in the same manner as in the above example. The conditions for laser irradiation at that time are the same as above. Then, by this laser irradiation, the n-source region and drain region 15 of the n-channel transistor are formed by diffusion from the sSG film 10', and the p-source region and drain region 16 of the p-channel transistor are formed by the BSG film. 11 regions are formed simultaneously by diffusion, and these regions are formed extremely finely and with high precision.
以上のような形成方法によれば、パターンニングがＡｓ
５Ｇ膜の１回、だけとなり、ソースおよびドレイン領域
の形成処理が１回になって工程が短縮され、且つ、極め
て短時間の１回だけの加熱によって形成するため辷、ソ
ースおよびドレイン領域が精度良く微細に形成すること
ができる。According to the above-described forming method, the patterning is performed using As.
The 5G film is formed only once, and the source and drain regions are formed only once, which shortens the process. Furthermore, since the formation process is performed only once in an extremely short time, the thickness, source and drain regions can be formed with high precision. It can be formed finely.
なお、第１図で説明した実施例において、ＢＳＣ膜を被
着して、ｐチャネルトランジスタ形成領域上を被覆した
後、ＡｓＨ３ガスを含むガス雰囲気でレーザ照射しても
同様の結果が得られる。In the embodiment described in FIG. 1, the same result can be obtained even if the BSC film is deposited to cover the p-channel transistor formation region and then laser irradiation is performed in a gas atmosphere containing AsH3 gas.
［発明の効果］
上記のＣ−ＭＯＳ ）ランジスタの実施例から明らかな
ように、本発明によれば一導電型不純物領域と異種導電
型不純物領域とを同時に画定することができて、処理工
程が簡単になり、且つ、短縮されて、しかも、微細領域
が高精度に形成されて、ＩＣの品質向上、集積度の向上
に顕著に寄与するものである。[Effects of the Invention] As is clear from the above embodiment of the C-MOS transistor, according to the present invention, an impurity region of one conductivity type and an impurity region of a different conductivity type can be defined simultaneously, and the processing steps can be simplified. It is simple and shortened, and a fine region can be formed with high precision, which significantly contributes to improving the quality and degree of integration of ICs.
第１図（ａ）、 （ｂｌおよび第２図（ａ）、 （ｂ）
は本発明にかかる形成方法の工程順断面図、
第３図はＣ−ＭＯＳ ｌ−ランジスタの断面概要図、第
４図（ａ）〜（Ｃ）は従来の形成方法の工程順断面図で
ある。
図において、
■はｐ−シリコン基板、２はｎ−ウェル領域、３はフィ
ールド絶縁膜、４はゲート電極、５．１５はｎ−ソース
領域およびドレイン領域、６．１６はｐ−ソース領域お
よびドレイン領域、７．８はレジスト膜マスク、
１０はＡｓ５Ｇ膜、 １１はＢＳＧ膜斗要明１−
２１Ｊ−ｊ化ＩＳ形代方池６エ科喉図第２図Figure 1 (a), (bl and Figure 2 (a), (b)
3 is a schematic cross-sectional view of a C-MOS l-transistor, and FIGS. 4(a) to (C) are cross-sectional views of a conventional forming method in the order of steps. . In the figure, 2 is a p-silicon substrate, 2 is an n-well region, 3 is a field insulating film, 4 is a gate electrode, 5.15 is an n-source region and drain region, and 6.16 is a p-source region and drain. area, 7.8 is the resist film mask, 10 is the As5G film, 11 is the BSG film 1-
21J-j IS Katashirokataike 6E Family Throat Diagram Figure 2
Claims (2)
上に配置し、且つ、異種導電型不純物ガスを含む雰囲気
中に異種導電型不純物形成領域を露出させ、全面にレー
ザを照射して前記固体不純物源とガス不純物源とから同
時に拡散させて一導電型不純物領域と異種導電型不純物
領域とを画定する工程が含まれてなることを特徴とする
半導体装置の製造方法。(1) A solid impurity source of one conductivity type is placed over an impurity formation region of one conductivity type, and the impurity formation region of a different conductivity type is exposed in an atmosphere containing an impurity gas of a different conductivity type, and the entire surface is irradiated with a laser. A method for manufacturing a semiconductor device, comprising the step of simultaneously diffusing from the solid impurity source and the gas impurity source to define an impurity region of one conductivity type and an impurity region of a different conductivity type.
上に配置し、且つ、異種導電型固体不純物源を異種導電
型不純物形成領域上に配置し、全面にレーザを照射して
前記２つの固体不純物源から同時に拡散させて一導電型
不純物領域と異種導電型不純物領域とを画定する工程が
含まれてなることを特徴とする半導体装置の製造方法。(2) One conductivity type facepiece impurity source is placed on the one conductivity type impurity formation region, and a different conductivity type solid impurity source is placed on the different conductivity type impurity formation region, and the entire surface is irradiated with laser to 1. A method of manufacturing a semiconductor device, comprising the step of simultaneously diffusing from two solid impurity sources to define an impurity region of one conductivity type and an impurity region of a different conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13939387A JPS63302518A (en) | 1987-06-02 | 1987-06-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13939387A JPS63302518A (en) | 1987-06-02 | 1987-06-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63302518A true JPS63302518A (en) | 1988-12-09 |
Family
ID=15244248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13939387A Pending JPS63302518A (en) | 1987-06-02 | 1987-06-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63302518A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997002594A1 (en) * | 1995-07-03 | 1997-01-23 | Intel Corporation | Low damage source and drain doping technique |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5236468A (en) * | 1975-09-18 | 1977-03-19 | Fujitsu Ltd | Shallow diffusion method |
| JPS5488780A (en) * | 1977-12-26 | 1979-07-14 | Cho Lsi Gijutsu Kenkyu Kumiai | Method of fabricating complementary mos transistor |
| JPS5552221A (en) * | 1978-10-12 | 1980-04-16 | Toshiba Corp | Impurity dispersion method and its device |
-
1987
- 1987-06-02 JP JP13939387A patent/JPS63302518A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5236468A (en) * | 1975-09-18 | 1977-03-19 | Fujitsu Ltd | Shallow diffusion method |
| JPS5488780A (en) * | 1977-12-26 | 1979-07-14 | Cho Lsi Gijutsu Kenkyu Kumiai | Method of fabricating complementary mos transistor |
| JPS5552221A (en) * | 1978-10-12 | 1980-04-16 | Toshiba Corp | Impurity dispersion method and its device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997002594A1 (en) * | 1995-07-03 | 1997-01-23 | Intel Corporation | Low damage source and drain doping technique |
| KR100381769B1 (en) * | 1995-07-03 | 2003-08-19 | 인텔 코오퍼레이션 | Low damage doping technique for self-aligned source and drain regions |
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