KR940016706A - Semiconductor package - Google Patents

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Publication number
KR940016706A
KR940016706A KR1019920027634A KR920027634A KR940016706A KR 940016706 A KR940016706 A KR 940016706A KR 1019920027634 A KR1019920027634 A KR 1019920027634A KR 920027634 A KR920027634 A KR 920027634A KR 940016706 A KR940016706 A KR 940016706A
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KR
South Korea
Prior art keywords
semiconductor package
adhesive
die pad
lead frame
holes
Prior art date
Application number
KR1019920027634A
Other languages
Korean (ko)
Inventor
정현조
송병석
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019920027634A priority Critical patent/KR940016706A/en
Priority to JP5298001A priority patent/JPH06232326A/en
Publication of KR940016706A publication Critical patent/KR940016706A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

이 발명은 반도체 패키지에 관한 것이다. 종래의 다이패드 밑면에 딤플을 형성하거나 관통홀을 형성한 패키지의 경우에 다이패드와 몰드 수지와의 결합력 약 화, 패키지 클랙의 유발, 다이접착공정에서 접착제가 외부로 과다하게 흘러넘쳐 신뢰성에 문제가 있다.This invention relates to a semiconductor package. In the case of a package in which a dimple is formed on the bottom of a conventional die pad or a through hole is formed, the bonding strength between the die pad and the mold resin is weakened, the package crack is caused, and the adhesive overflows to the outside in the die bonding process, resulting in reliability problems. There is.

이 발명은 다이패드에 모자이크 모양으로 형성된 다수개의 관통홀과, 상기 다수개의 관통홀이 배열되어 있는 부분이 상기 다이패드 상면보다 낮게 함몰되어 형성되는 스웨징 공간과, 상기 스웨징 공간의 외주면에 소정폭을 갖는 단턱을 구비하는 리드 프레임을 사용한 반도체 패키지를 제공한다.According to the present invention, a plurality of through holes formed in a mosaic shape in a die pad, a swaging space formed by recessing a portion where the plurality of through holes are arranged lower than an upper surface of the die pad, and a predetermined outer peripheral surface of the swaging space are provided. A semiconductor package using a lead frame having a stepped width is provided.

이 발명은 리드 프레임과 몰드수지 사이의 접착력을 향상시키고, 다이접착공정에서 접착제의 흘러넘침을 방지하여 생산성 향상 및 원가 절감을 할 수 있다.The present invention can improve the adhesive force between the lead frame and the mold resin, and prevent the overflow of the adhesive in the die bonding process can improve productivity and reduce the cost.

Description

반도체 패키지Semiconductor package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 3 도(가) 및 (나)는 이 발명에 따른 반도체 패키지에 이용되는 리드프레임의 평면도 및 A-A선단면도, 제 4 도(가) 및 (나)는 이 발명의 실시예에 따른 반도체 패키지의 단면도 및 요부 확대도이다.3A and 3B are a plan view and an AA cross-sectional view of a lead frame used in the semiconductor package according to the present invention, and FIGS. 4A and 4B are views of the semiconductor package according to the embodiment of the present invention. It is sectional drawing and a main part enlarged view.

Claims (7)

다이패드와 다수개의 리드를 구비한 리드 프레임과, 상기 다이패드 상에 접착제를 매개하여 탑재된 반도체 칩과, 상기 반도체 칩과 상기 다수개의 리드를 결선하는 다수개의 본딩와이어로 결선되고, 상기 다수개의 리드 일부를 제외한 상기구조 전체를 봉합하는 몰딩수지로 구성된 반도체 패키지에 있어서, 상기 리드 프레임은 다이패드에 모자이크 모양으로 형성된 다수개의 관통홀과, 상기 다수개의 관통홀이 배열되어 있는 부분이 상기 다이패드 상면보다 낮게 함몰되어 형성되는 스웨징공간과, 상기 스웨징 공간의 외주면에 소정폭을 갖는 단턱을 구비하는 것을 특징으로 하는 반도체 패키지.A lead frame having a die pad and a plurality of leads, a semiconductor chip mounted on the die pad via an adhesive, a plurality of bonding wires connecting the semiconductor chip and the plurality of leads, A semiconductor package including a molding resin for sealing the entire structure except a part of a lead, wherein the lead frame includes a plurality of through holes formed in a mosaic shape on a die pad and a portion in which the plurality of through holes are arranged. And a swaging space formed to be recessed lower than an upper surface, and a stepped portion having a predetermined width on an outer circumferential surface of the swaging space. 제 1 항에 있어서, 상기 접착제는 상기 단턱상부에 형성된 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the adhesive is formed on the stepped portion. 제 1 항 또는 제 2 항에 있어서, 상기 접착제는 에폭시 수지계 또는 폴리이미드 수지계로서 온이나 실리카, 알루미늄 필터등을 첨가한 합성 수지인 것을 특징으로 하는 반도체 패키지.The semiconductor package according to claim 1 or 2, wherein the adhesive is an epoxy resin or a polyimide resin, and a synthetic resin added with warm, silica, aluminum filters and the like. 제 1 항에 있어서, 상기 관통홀은 그 모양이 원형 또는 다각형 모양으로 형성된 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the through hole has a circular or polygonal shape. 제 1 항에 있어서, 상기 몰드수지는 상기 관통홀을 통하여 상기 스웨징 공간내에 채워진 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the mold resin is filled in the swaging space through the through hole. 제 1 항에 있어서, 상기 단턱은 접착제가 흘러넘치는 것을 방지하는 역할을 하는 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the step serves to prevent the adhesive from spilling. 제 1 항에 있어서, 상기 리드 프레임은 스탬핑 가공이 가능한 재료로 이루어진 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the lead frame is made of a material capable of stamping. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920027634A 1992-12-31 1992-12-31 Semiconductor package KR940016706A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019920027634A KR940016706A (en) 1992-12-31 1992-12-31 Semiconductor package
JP5298001A JPH06232326A (en) 1992-12-31 1993-11-29 Package for semiconductor device and its preparation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920027634A KR940016706A (en) 1992-12-31 1992-12-31 Semiconductor package

Publications (1)

Publication Number Publication Date
KR940016706A true KR940016706A (en) 1994-07-23

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ID=19348833

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920027634A KR940016706A (en) 1992-12-31 1992-12-31 Semiconductor package

Country Status (2)

Country Link
JP (1) JPH06232326A (en)
KR (1) KR940016706A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1024532A3 (en) * 1999-01-28 2001-04-18 Fujitsu Limited Semiconductor device and method of producing the same
JP4055158B2 (en) 2003-05-28 2008-03-05 ヤマハ株式会社 Lead frame and semiconductor device provided with lead frame

Also Published As

Publication number Publication date
JPH06232326A (en) 1994-08-19

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